Abstract: A semiconductor structure includes a die including a surface, a lid disposed over the surface of the die, and a thermally conductive material disposed between the die and the lid, wherein the lid includes a protrusion protruded towards the surface of the die and the thermally conductive material surrounds the protrusion. Also, a method of manufacturing a semiconductor structure includes providing a die including a surface, providing a lid, removing a portion of the lid to form a protrusion, disposing a thermally conductive material between the surface of the die and the lid, wherein the protrusion of the lid is surrounded by the thermally conductive material. Further, an apparatus for manufacturing a semiconductor structure and a method of manufacturing a semiconductor structure by the apparatus are disclosed.

Abstract: A semiconductor packaging device includes: a first chip disposed separately from the first chip on a substrate; a second chip disposed on the substrate, wherein the first chip and the second chip comprise a first heat energy producing rating and a second heat energy producing rating, respectively, the first heat energy producing rating is different from the second heat energy producing rating; and a heat sink arranged in thermal communication with the first chip and the second chip, wherein the heat sink is arranged to have a first slot configured substantially along a separation region between the first chip and the second chip.

Abstract: A semiconductor structure includes a die including a surface, a lid disposed over the surface of the die, and a thermally conductive material disposed between the die and the lid, wherein the lid includes a protrusion protruded towards the surface of the die and the thermally conductive material surrounds the protrusion. Also, a method of manufacturing a semiconductor structure includes providing a die including a surface, providing a lid, removing a portion of the lid to form a protrusion, disposing a thermally conductive material between the surface of the die and the lid, wherein the protrusion of the lid is surrounded by the thermally conductive material. Further, an apparatus for manufacturing a semiconductor structure and a method of manufacturing a semiconductor structure by the apparatus are disclosed.

Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.

Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

Abstract: A semiconductor packaging device includes: a first chip disposed separately from the first chip on a substrate; a second chip disposed on the substrate, wherein the first chip and the second chip comprise a first heat energy producing rating and a second heat energy producing rating, respectively, the first heat energy producing rating is different from the second heat energy producing rating; and a heat sink arranged in thermal communication with the first chip and the second chip, wherein the heat sink is arranged to have a first slot configured substantially along a separation region between the first chip and the second chip.

Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the reinforcement plate to the die.

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract: One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an interface between the substrate and one or more semiconductor chips in a package. In an embodiment the heat pipe may be positioned on a side of the substrate opposite the semiconductor chip and through-substrate vias may be utilized to dissipate heat through the substrate. In an alternative embodiment, the heat pipe may be positioned on a same side of the substrate as the semiconductor chip and may be thermally connected to the one or more semiconductor chips.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective.

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

Abstract: A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective.

Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.

Abstract: An embodiment package includes a first fan-out tier, fan-out redistribution layers (RDLs) over the first fan-out tier, and a second fan-out tier over the fan-out RDLs. The first fan-out tier includes one or more first device dies and a first molding compound extending along sidewalls of the one or more first device dies. The second fan-out tier includes one or more second device dies bonded to fan-out RDLs, a dummy die bonded to the fan-out RDLs, and a second molding compound extending along sidewalls of the one or more second device dies and the dummy die. The fan-out RDLs electrically connects the one or more first device dies to the one or more second device dies, and the dummy die is substantially free of any active devices.

Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.