Patents by Inventor Cheng-chieh Hsieh

Cheng-chieh Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9034695
    Abstract: A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20140361432
    Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Shang-Yun Hou, Jing-Cheng Lin, Shin-Puu Jeng
  • Patent number: 8901735
    Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ying Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Jing-Cheng Lin, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 8865521
    Abstract: A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Kim Hong Chen, Shang-Yun Hou, Chao-Wen Shih, Cheng-Chieh Hsieh, Chen-Hua Yu
  • Publication number: 20140264803
    Abstract: Methods and apparatus are disclosed for forming ultra-thin packages for semiconductor devices on flexible substrates. A flexible substrate may comprise a plurality of insulating layers and redistribution layers. Openings of the flexible substrate may be formed at one side of the flexible substrate, two sides of the flexible substrate, or simply cut through the flexible substrate to divide the flexible substrate into two parts. Connectors may be placed within the opening of the flexible substrate and connected to redistribution layers of the flexible substrate. Dies can be attached to the connectors and electrically connected to the connectors and to the redistribution layers of the flexible substrate. Structure supports may be placed at another side of the flexible substrate on the surface or within an opening.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: Tsung-Shu Lin, Cheng-Chieh Hsieh, Hung-An Teng, Sao-Ling Chiu, Shang-Yun Hou
  • Publication number: 20140264698
    Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.
    Type: Application
    Filed: June 27, 2013
    Publication date: September 18, 2014
    Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Bruce C.S. Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh
  • Patent number: 8836094
    Abstract: Methods and apparatus are disclosed for forming ultra-thin packages for semiconductor devices on flexible substrates. A flexible substrate may comprise a plurality of insulating layers and redistribution layers. Openings of the flexible substrate may be formed at one side of the flexible substrate, two sides of the flexible substrate, or simply cut through the flexible substrate to divide the flexible substrate into two parts. Connectors may be placed within the opening of the flexible substrate and connected to redistribution layers of the flexible substrate. Dies can be attached to the connectors and electrically connected to the connectors and to the redistribution layers of the flexible substrate. Structure supports may be placed at another side of the flexible substrate on the surface or within an opening.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Cheng-Chieh Hsieh, Hung-An Teng, Sao-Ling Chiu, Shang-Yun Hou
  • Publication number: 20140252591
    Abstract: A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the reinforcement plate to the die.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Cheng-Chieh Hsieh, Tsung-Shu Lin
  • Patent number: 8816498
    Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Shang-Yun Hou, Jing-Cheng Lin, Shin-Puu Jeng
  • Patent number: 8782593
    Abstract: A method includes retrieving a first component information of a secured portion of a package, wherein the first component information is encrypted. The step of retrieving includes decrypting the first component information. A thermal resistance-network (R-network) is generated from the decrypted first component information. A temperature map of the package is generated using the thermal R-network and a second component information of an unsecured portion of the package, wherein the secured portion and the unsecured portion are bonded to each other.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Min Fu, Wan-Yu Lo, Meng-Fu You, Po-Hsiang Huang, Cheng-Chieh Hsieh
  • Publication number: 20140131864
    Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
    Type: Application
    Filed: January 22, 2014
    Publication date: May 15, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Ying Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Jing-Cheng Lin, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20140119029
    Abstract: An illumination apparatus includes a substrate, a reflective cup, an illumination unit and a lens structure. The reflective cup is placed on the substrate, and includes a plurality of first fasteners. The first fasteners are placed on the outer surface of the reflective cup. The illumination unit is mounted on the substrate within the reflective cup. The lens structure covers the reflective cup, and includes a plurality of second fasteners. The second fasteners can be removably engaged with the first fasteners, so that the lens structure can be fastened on the reflective cup.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 1, 2014
    Applicant: Lextar Electronics Corporation
    Inventor: Cheng-Chieh HSIEH
  • Publication number: 20140089876
    Abstract: A method includes retrieving a first component information of a secured portion of a package, wherein the first component information is encrypted. The step of retrieving includes decrypting the first component information. A thermal resistance-network (R-network) is generated from the decrypted first component information. A temperature map of the package is generated using the thermal R-network and a second component information of an unsecured portion of the package, wherein the secured portion and the unsecured portion are bonded to each other.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Min Fu, Wan-Yu Lo, Meng-Fu You, Po-Hsiang Huang, Cheng-Chieh Hsieh
  • Patent number: 8664760
    Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Ying-Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Jing-Cheng Lin
  • Publication number: 20140045332
    Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.
    Type: Application
    Filed: October 18, 2013
    Publication date: February 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chieh Hsieh, Hung-An Teng, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20140038405
    Abstract: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.
    Type: Application
    Filed: October 3, 2013
    Publication date: February 6, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Kuo-Ching Hsu, Cheng-Chieh Hsieh, Ying-Ching Shih, Po-Hao Tsai, Cheng-Lin Huang, Jing-Cheng Lin
  • Publication number: 20140015106
    Abstract: One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an interface between the substrate and one or more semiconductor chips in a package. In an embodiment the heat pipe may be positioned on a side of the substrate opposite the semiconductor chip and through-substrate vias may be utilized to dissipate heat through the substrate. In an alternative embodiment, the heat pipe may be positioned on a same side of the substrate as the semiconductor chip and may be thermally connected to the one or more semiconductor chips.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 16, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Way Lee Cheng, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 8610285
    Abstract: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Kuo-Ching Hsu, Cheng-Chieh Hsieh, Ying-Ching Shih, Po-Hao Tsai, Cheng-Lin Huang, Jing-Cheng Lin
  • Patent number: 8604619
    Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: December 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Hung-An Teng, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20130273694
    Abstract: A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 17, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Shang-Yun Hou, Shin-Pun Jeng