Patents by Inventor Cheng Chien

Cheng Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12288735
    Abstract: An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: April 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Min-Feng Ku, Yao-Chun Chuang, Cheng-Chien Li, Ching-Pin Lin
  • Publication number: 20250126758
    Abstract: The present invention provides a rear-door heat dissipation system with a horizontally arranged and series-connected design comprising a heat dissipation cabinet, at least one condenser unit, and a heat dissipation device. The heat dissipation cabinet is provided therein with an active heat source device and a cabinet back door on one side of the heat dissipation cabinet, wherein the cabinet back door is provided with an air circulation unit. The condenser unit is provided on the cabinet back door, comprising a plurality of condensers. Wherein the circulation tube system of each of the condensers comprises a first and second main-channel aluminum tube, and aluminum flat tubes. Each aluminum flat tube has two ends respectively connecting to the first and second main-channel aluminum tube. An airflow channel is formed between each two adjacent aluminum flat tubes to enable air circulation, and each airflow channel is provided with an aluminum fin.
    Type: Application
    Filed: September 3, 2024
    Publication date: April 17, 2025
    Inventors: Cheng-Chien WAN, Cheng-Jui WAN, Chun-Hsien SU, Hui-Fen HUANG, Fong Jou TU, Chi Cheng CHEN, Chuan Meng WANG
  • Publication number: 20250126818
    Abstract: An IC structure and methods of forming the same are described. In some embodiments, the structure includes a fin structure disposed over a substrate, the fin structure includes first and second segments and a bottom surface between the first and second segments, and the bottom surface includes a plurality of recesses. The structure further includes a dielectric material disposed between the first and second segments of the fin structure, and the dielectric material is disposed on the bottom surface and in the plurality of recesses. The structure further includes a gate structure disposed over the first segment of the fin structure, and the gate structure covers a top surface and side surfaces of the first segment of the fin structure.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 17, 2025
    Inventors: Yuying HSIEH, Cheng-Chien LI, Huei-Shan WU
  • Publication number: 20250113419
    Abstract: A display device and a brightness adjustment method thereof are provided. The display device includes multiple light panels and a control circuit. Each light panel includes multiple light-emitting diodes, a driving circuit, and a storage circuit. The driving circuit is used to drive the light-emitting diodes and detect a forward voltage value of at least one light-emitting diode among the light-emitting diodes as a forward voltage value of a corresponding light panel. When a target light panel is used to replace one of the light panels, the control circuit controls forward voltage values of the target light panel and the reference light panel to become consistent.
    Type: Application
    Filed: August 30, 2024
    Publication date: April 3, 2025
    Applicant: Optoma Corporation
    Inventors: Yi-Cheng Liu, Yen-Hsiang Hung, Cheng-Chien Ou
  • Publication number: 20250107040
    Abstract: The present invention provides an immersion heat exchange system comprising cooling equipment and heat exchange equipment connected to the cooling equipment. The cooling equipment comprises a primary container and at least one cooling tank provided in the primary container. The cooling tank holds a cooling liquid for an active heat source device to be immersed in the cooling liquid. The heat exchange equipment comprises a secondary container and at least one heat exchange tank provided in the secondary container. The heat exchange tank provided therein with at least one condenser. The condenser divides the heat exchange tank into an input portion and an output portion. There is at least one circulation device corresponding to and working with the input portion and/or the output portion of the heat exchange tank to make the cooling liquid exchanged and circulated between the cooling tank and the heat exchange tank.
    Type: Application
    Filed: May 8, 2024
    Publication date: March 27, 2025
    Inventors: CHENG-CHIEN WAN, CHENG-JUI WAN, CHUN-HSIEN SU, HUI-FEN HUANG, FONG JOU TU, CHI CHENG CHEN, CHUAN MENG WANG
  • Publication number: 20250107041
    Abstract: A heat exchanger module for immersion cooling system includes cooling equipment and heat exchange equipment connected to the cooling equipment. The cooling equipment includes a primary container and at least one cooling tank provided in the primary container. The cooling tank holds a cooling liquid for an active heat source device to be immersed in the cooling liquid. The heat exchange equipment includes a secondary container and at least one heat exchange tank provided in the secondary container. The heat exchange tank is provided therein with at least one condenser. The condenser divides the heat exchange tank into an input portion and an output portion. There is at least one circulation device corresponding to and working with the input portion and/or the output portion of the heat exchange tank to make the cooling liquid exchanged and circulated between the cooling tank and the heat exchange tank.
    Type: Application
    Filed: September 12, 2024
    Publication date: March 27, 2025
    Inventors: Cheng-Chien WAN, Cheng-Jui WAN, Chun-Hsien SU, Hui-Fen HUANG, Fong Jou TU, Chi Cheng CHEN, Chuan Meng WANG
  • Patent number: 12253313
    Abstract: A heat dissipation device for a multipoint heat source includes an evaporator unit and a condenser unit. The evaporator unit includes a multi-channel duct. At least one narrow side of the multi-channel duct has a communication opening in communication with the bottom side of at least one tube of the condenser unit, and a wide side of the multi-channel duct is attached to the multipoint heat source so that a heat conduction medium can be circulated through the evaporator unit and the condenser unit while alternating between a liquid phase and a gaseous phase.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 18, 2025
    Assignee: MAN ZAI INDUSTRIAL CO., LTD.
    Inventors: Cheng-Chien Wan, Cheng-Rui Wan, Chun-Hsien Su, Hui-Fen Huang, Fong Jou Tu, Chi Cheng Chen, Chuan Meng Wang
  • Patent number: 12237380
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Publication number: 20250048452
    Abstract: Various schemes pertaining to coordinated time-division multiple-access (C-TDMA) protocols, transmission opportunity (TXOP) sharing modes for time allocation, and exchange of parameters in multi-access point (multi-AP) systems are described. An apparatus (e.g., a sharing access point (AP)) acquires a TXOP. The apparatus also triggers one or more shared APs to participate in C-TDMA communications with respectively associated stations (STAs) within the TXOP.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 6, 2025
    Inventors: Samat Shabdanov, Po-Chun Fang, Cheng-Chien Su, James Chih-Shi Yee, Chien-Fang Hsu, You-Wei Chen, Chung-Ta Ku, Weisung Tsao, Po-Yuen Cheng
  • Publication number: 20240421893
    Abstract: A UE and a method for handling a cell reselection procedure are provided. The method receives, from a camped cell, information related to the cell reselection procedure. The method determines whether the camped cell operates on a first frequency range for a Non-Terrestrial Network (NTN) operation. The method performs a measurement, for the cell reselection procedure for selecting a suitable cell, based on the information related to the cell reselection procedure after determining that the camped cell operates on the first frequency range for the NTN operation.
    Type: Application
    Filed: September 30, 2022
    Publication date: December 19, 2024
    Inventors: MING-HUNG TAO, CHENG CHIEN-CHUN, LIN CHIA-HUNG, TSENG YUNG-LAN, CHEN HUNG-CHEN
  • Publication number: 20240387410
    Abstract: The present disclosure describes a semiconductor structure including a TSV in contact with a substrate and a metal ring structure laterally surrounding the TSV. The metal ring structure includes one or more metal rings arranged as a stack and one or more metal vias interposed between two adjacent metal rings of the one or more metal rings. The metal ring structure is electrically coupled to the substrate through one or more conductive structures.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chang CHEN, Kun-Hsiang LIN, Cheng-Chien LI
  • Publication number: 20240379588
    Abstract: Integrated circuit (IC) structures and methods for forming the same are provided. An IC structure according to the present disclosure includes a substrate, an interconnect structure over the substrate, a guard ring structure disposed in the interconnect structure, a via structure vertically extending through the guard ring structure, and a top metal feature disposed directly over and in contact with the guard ring structure and the via structure. The guard ring structure includes a plurality of guard ring layers. Each of the plurality of guard ring layers includes a lower portion and an upper portion disposed over the lower portion. Sidewalls of the lower portions and upper portions of the plurality of guard ring layers facing toward the via structure are substantially vertically aligned to form a smooth inner surface of the guard ring structure.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Min-Feng Ku, Yao-Chun Chuang, Cheng-Chien Li, Ching-Pin Lin
  • Publication number: 20240379660
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • Patent number: 12136600
    Abstract: The present disclosure describes a semiconductor structure including a TSV in contact with a substrate and a metal ring structure laterally surrounding the TSV. The metal ring structure includes one or more metal rings arranged as a stack and one or more metal vias interposed between two adjacent metal rings of the one or more metal rings. The metal ring structure is electrically coupled to the substrate through one or more conductive structures.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: November 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chang Chen, Kun-Hsiang Lin, Cheng-Chien Li
  • Publication number: 20240357680
    Abstract: A multi-link operation (MLO) Wi-Fi dual traffic identification data transmission method is adopted for an MLO Wi-Fi access point (AP) and an MLO Wi-Fi client. The method includes linking the MLO Wi-Fi client to the MLO Wi-Fi access point (AP) with a first link and a second link, rendering traffic in the first link a first block acknowledgement (BA) window with a first traffic identification (TID), rendering traffic in the second link a second block acknowledgement (BA) window with a second traffic identification (TID), using the first block acknowledgement (BA) window with the first TID to transmit data through the first link, and using the second block acknowledgement (BA) window with the second TID to transmit data through the second link.
    Type: Application
    Filed: April 3, 2024
    Publication date: October 24, 2024
    Applicant: MEDIATEK INC.
    Inventors: Tsung-Jung Lee, Ying-You Lin, Cheng-Chien Su, Kuo-Wei Chen
  • Patent number: 12125460
    Abstract: A system that can intelligently help a user judge the resolution requirement of the image content. In an example, the display panel can show in different virtual resolutions or the system can automatically judge whether the image content requires high or low resolution using a similarity judgement. The system can then inform the display panel what virtual resolution should be shown or what the optimal resolution is using the similarity judgment and send the image content to the display panel with that resolution.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: October 22, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hsing-Hung Hsieh, Cheng-Chien Chen, Kuan-Ting Wu
  • Publication number: 20240332218
    Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Inventors: Min-Feng KU, Yao-Chun CHUANG, Ching-Pin LIN, Cheng-Chien LI
  • Publication number: 20240332219
    Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Inventors: Min-Feng KU, Yao-Chun CHUANG, Ching-Pin LIN, Cheng-Chien LI
  • Publication number: 20240274669
    Abstract: An IC structure includes a semiconductor substrate; an isolation structure formed in the semiconductor substrate, thereby defining active regions surrounded by the isolation feature; a first well of a first conductivity type formed in the semiconductor substrate; a neutral region formed in the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type formed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; a source disposed on the second well of the semiconductor substrate; a drain disposed on the first well of the semiconductor substrate; and a gate structure interposed between the source and the drain. The gate structure is engaging the first well, the neutral region and the second well of the semiconductor substrate. The source, the drain and the gate structure are configured as a FET.
    Type: Application
    Filed: July 14, 2023
    Publication date: August 15, 2024
    Inventors: YuYing Hsieh, Cheng-Chien Li, Huei-Shan Wu
  • Patent number: 12046566
    Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Feng Ku, Yao-Chun Chuang, Ching-Pin Lin, Cheng-Chien Li