Patents by Inventor Cheng Chou

Cheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130126128
    Abstract: The method of manufacturing heat pipe is disclosed to insert a center bar into a metal tube such that the center bar contacts a clearance area of the inner sidewall of the metal tube. Then, the method is to fill the interval between the center bar and the metal tube with powder for sintering. At last, the method is to perform a sintering, extract the center bar, inject working fluid, and close the metal tube. A heat pipe is therefore formed. Because of no sintered powder on the clearance area, the heat pipe can be bent at the clearance area without damaging the capillary structure formed by the sintered powder. The flow path of the working fluid is not interrupted or influenced, so the heat transfer efficiency can be maintained, which overcomes the decrement of the heat transfer efficiency of a bent heat pipe in the prior art.
    Type: Application
    Filed: August 7, 2012
    Publication date: May 23, 2013
    Inventor: Wei-Cheng Chou
  • Publication number: 20130128995
    Abstract: A method includes generating representative noise variance estimates based on a plurality of received symbols received in an orthogonal frequency division multiplexing (OFDM) signal. The representative noise variance estimates correspond to respective frequency intervals of a plurality of frequency intervals of the OFDM channel. Individual frequency intervals of the plurality of frequency intervals include a plurality of contiguous frequency bins of the OFDM signal.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Inventors: Cimarron Mittelsteadt, Cheng-Chou Lan
  • Publication number: 20130128822
    Abstract: A carrier tracking technique includes allocating a first number of bits per symbol to a carrier tracking subcarrier of a plurality of subcarriers of an orthogonal frequency division multiplexing (OFDM) signal based on a first target performance margin. The technique includes allocating numbers of bits per symbol to other subcarriers of the plurality of subcarriers based on a second target performance margin.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Inventors: Cimarron Mittelsteadt, Cheng-Chou Lan
  • Patent number: 8439632
    Abstract: A thermal module includes a fan device having a fan and a fan housing for covering the fan. A vent is disposed on the fan housing. The thermal module further includes an airflow guiding device installed on the fan housing and disposed on a side of the vent for guiding airflow into the vent.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: May 14, 2013
    Assignee: Wistron Corporation
    Inventor: Wei-Cheng Chou
  • Patent number: 8437215
    Abstract: A memory comprises a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells. A first word line segment driver is connected to the first plurality of bits cells. A second word line segment driver is connected to the second plurality of bits cells. The first and second word line segment drivers are selectively operable for activating one of the first and second pluralities of bit cells at a time to the exclusion of the other plurality of bit cells. A shared sense amplifier is coupled to at least one of the first plurality of bit cells and at least one of the second plurality of bit cells. The shared sense amplifier is configured to receive signals from whichever of the one first or second bit cell is activated by its respective word line segment driver at a given time.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: May 7, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chiting Cheng, Hsiu-Feng Peng, Ming-Zhang Kuo, Chung-Cheng Chou
  • Publication number: 20130101389
    Abstract: The invention provides a heat-dissipating system and a control method thereof. The heat-dissipating system has a plurality of fans and is configured for adjusting rotation-speeds of the fans. The control method includes following steps: obtaining a plurality of rotation-speed values of the fans; computing out a rotation-speed reference value according to the rotation-speed values; when the rotation-speed reference value is greater than a first threshold value, decreasing the rotation-speeds of the fans through a corresponding fan control signal; when the rotation-speed reference value is less than a second threshold value, increasing the rotation-speeds of the fans through the corresponding fan control signal.
    Type: Application
    Filed: July 16, 2012
    Publication date: April 25, 2013
    Applicant: CORETRONIC CORPORATION
    Inventors: Chih-Cheng Chou, Wen-Hsien Su, Tsung-Ching Lin, Chao-Nan Chien
  • Publication number: 20130100730
    Abstract: A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 25, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jonathan Tsung-Yung CHANG, Chiting CHENG, Chien-Kuo SU, Chung-Cheng CHOU, Jack LIU
  • Patent number: 8416002
    Abstract: A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: April 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Liu, Chung-Cheng Chou, Yi-Tzu Chen
  • Patent number: 8405441
    Abstract: A latch circuit includes an output driver electrically coupled with a circuit. The circuit is electrically coupled with the output driver through a first path and a second path. The circuit is configured to receive a data signal. The circuit is configured to divert a signal of the output driver through the first path at a falling edge of the data signal. The circuit is configured to divert the signal of the output driver through the second path at a rising edge of the data signal.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Kuo Su, Yi-Tzu Chen, Chung-Cheng Chou
  • Publication number: 20130062774
    Abstract: A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.
    Type: Application
    Filed: September 8, 2011
    Publication date: March 14, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chia-Cheng Chou, Shing-Chyang Pan, Keng-Chu Lin, Shwang-Ming Jeng
  • Publication number: 20130051128
    Abstract: The propagation delay of a signal through multiple load devices coupled sequentially along a conductor is improved by separating a subset of the load devices that is more distant from the signal source, and coupling the more distant subset to the signal through a fly-over conductor that bypasses the subset that is nearer to the signal source. The technique is applicable to subsets of bit cells in a random access memory (SRAM) coupled to a given word line, or to word line decoder gates coupled sequentially to a strobe signal, as well as other circuits wherein load devices selectable as a group can be divided into subsets by proximity to the signal source. In an SRAM layout with multiple levels, different metal deposition layers carry the conductor legs between the load devices versus the fly-over conductor bypassing the nearer subset.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Wen Lu, Wei-Jer Hsieh, Chiting Cheng, Chung-Cheng Chou, Jonathan Tsung-Yung Chang
  • Publication number: 20130052755
    Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Publication number: 20130042477
    Abstract: The disclosure provides a method for fabricating a heat pipe, and an instrument of the method. The method for fabricating a heat pipe includes providing a hollow tube, wherein the hollow tube has an open end and a closed end; disposing a mandril into the hollow tube from the open end, wherein the inside wall of the hollow tube is separated from the mandril by a space, and wherein the mandril comprises a first portion and a second portion and the first portion has a thermal expansion coefficient larger than that of the second portion; filling up the space between the mandril and the hollow tube with a powder; performing a sintering process to the hollow tube, forming a first agglomeration region and a second agglomeration region; removing the mandril; injecting a working fluid into the hollow tube; and sealing the open end of the hollow tube.
    Type: Application
    Filed: June 28, 2012
    Publication date: February 21, 2013
    Applicant: WISTRON CORP.
    Inventor: Wei-Cheng Chou
  • Patent number: 8373991
    Abstract: The invention provides a metal thermal interface material (TIM) with through-holes in its body and/or zigzags or wave shapes on its border, which is suitable for use at thermal interfaces of a thermal conduction path from an integrated circuit die to its associated heat sink in a packaged microelectronic component. The invention also includes a thermal module and a packaged microelectronic component including the metal thermal interface material.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: February 12, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Yuan-Chang Fann, Chun-Mu Chen, Cheng-Chou Wong, Chih-Tsung Tu, Jen-Dong Hwang
  • Publication number: 20130023737
    Abstract: A non-invasive detecting apparatus and an operating method thereof are disclosed. The non-invasive detecting apparatus includes an elastic base, a detecting module, and a data processing module. The detecting module is disposed on the elastic base. The detecting module includes at least one detecting unit used to detect a tissue under a detected region of a detected object to obtain a detection information. The data processing module analyzes and processes the detection information to generate a detection result.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 24, 2013
    Inventors: Chung-Cheng Chou, William Wang, Chung-Ping Chuang, Meng-Shin Yen
  • Patent number: 8357988
    Abstract: A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: January 22, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Chou Hung, Victor-Chiang Liang, Jui-Meng Jao, Cheng-Hung Li, Sheng-Yi Huang, Tzung-Lin Li, Huai-Wen Zhang, Chih-Yu Tseng
  • Patent number: 8359528
    Abstract: A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: January 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Liu, Yi-Tzu Chen, Chung-Cheng Chou
  • Patent number: 8354346
    Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: January 15, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chia-Cheng Chou, Ming-Chung Liang, Keng-Chu Lin, Tzu-Li Lee
  • Publication number: 20130009741
    Abstract: The invention provides an integrated circuit transformer disposed on a substrate. The integrated circuit transformer includes a first coiled metal pattern disposed on the substrate, comprising an inner loop segment and an outer loop segment. A second coiled metal pattern is disposed on the substrate, laterally between the inner loop segment and the outer loop segment. A dielectric layer is disposed on the first coiled metal pattern and the second coiled metal pattern. A first via is formed through the dielectric layer, electrically connecting to one of the first and second coiled metal patterns. A first redistribution pattern is disposed on the dielectric layer, electrically connecting to and extending along the first via, wherein the first redistribution pattern covers at least a portion of the first coiled metal pattern and at least a portion of the second coiled metal pattern.
    Type: Application
    Filed: May 17, 2012
    Publication date: January 10, 2013
    Applicant: MEDIATEK INC.
    Inventors: Cheng-Chou HUNG, Cheng-Jyi CHANG, Tung-Hsing LEE, Wei-Che HUANG
  • Publication number: 20130002654
    Abstract: A three-dimensional (3D) glasses and a method for operating the same are provided. The 3D glasses includes a first lens, a second lens, an infrared receiver and a control unit. The infrared receiver receives an infrared signal to output a digital control signal. The control unit is coupled to the infrared receiver. The control unit controls a first state of the first lens and a second state of the second lens according to a first pulse of the digital control signal, where at least one of the first state and the second state is an OFF state.
    Type: Application
    Filed: April 1, 2012
    Publication date: January 3, 2013
    Applicant: CORETRONIC CORPORATION
    Inventors: Tse-Fan Yeh, Chen-Cheng Chou, Chun-Chieh Chen, Shu-Hui Liao, Jeng-An Liao, Chun-Hao Chen