Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.

Abstract: A method for controlling a fan in a fan start-up stage including a first time period and a second time period comprises the following steps of: during the first time period, continuously providing a first driving signal to drive the fan; and during the second time period, continuously providing a second driving signal to drive the fan; wherein, the signal value of the first driving signal gradually decreases until being equal to the signal value of the second driving signal. Wherein the signal value of the first driving signal non-linearly decreases, the signal value of the second driving signal is an unchanged value. Wherein, the first time period and the second time period are adjusted for a different fan but the sum of the first time period and the second time period is always the same. A fan is also disclosed.

Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.

Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.

Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.

Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.

Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dis

Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.

Abstract: A method for manufacturing fine-pitch bumps comprises the steps of providing a silicon substrate; forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first zones and a plurality of second zones; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer to form a plurality of opening slots; forming a plurality of copper bumps at the opening slots, wherein each of the copper bumps comprises a first top surface and a ring surface; heating the photoresist layer to form a plurality of body portions and a plurality of removable portions; etching the photoresist layer; and removing the second zones to enable each of the first zones to form an under bump metallurgy layer having a bearing portion and an extending portion.

Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.

Abstract: A semiconductor packaging method includes providing a substrate having a plurality of connection pads; mounting a chip on the substrate, wherein the chip comprises a plurality of copper-containing bumps directly coupled to the connection pads, and each of the copper-containing bumps comprises a ring surface; forming an anti-dissociation gel between the substrate and the chip, wherein the anti-dissociation gel comprises a plurality of anti-dissociation substances, and the ring surfaces of the copper-containing bumps are covered by the anti-dissociation substances.

Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dis

Abstract: A method for manufacturing fine-pitch bumps comprises the steps of providing a silicon substrate; forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first zones and a plurality of second zones; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer to form a plurality of opening slots; forming a plurality of copper bumps at the opening slots, wherein each of the copper bumps comprises a first top surface and a ring surface; heating the photoresist layer to form a plurality of body portions and a plurality of removable portions; etching the photoresist layer; and removing the second zones to enable each of the first zones to form an under bump metallurgy layer having a bearing portion and an extending portion.

Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dis

Abstract: A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots corresponded to the first areas of the titanium-containing metal layer, forming a plurality of copper bumps at the opening slots, proceeding a heat procedure, forming a plurality of bump isolation layers on the copper bumps, forming a plurality of connective layers on the bump isolation layers, removing the photoresist layer, removing the second areas and enabling each the first areas to form an under bump metallurgy layer.

Abstract: An organic electroluminescent display panel, which comprises a substrate, at least one display structure area, at least one first dummy area, and at least one second dummy area. The display structure area comprises at least one encapsulation area, at least one pixel area, a first conducting area, a second conducting area, a wiring area, a first connecting area, and a second connecting area. The wiring area and the first dummy area connect the first connecting area, and the two conducting areas and the second dummy area connect the second connecting area. Besides, the first and the second connecting areas overlap a selected part of the encapsulation area of a neighboring display structure area. Accordingly, the number and capacity of display structure areas on the organic electroluminescent display panel are increased to obtain a uniform brightness during a lighting test.

Abstract: A full-color OLED display panel comprises a full-color organic light-emitting device and a colored filter device stacked on the light-exit surface of the full-color organic light-emitting device. The full-color organic light-emitting device comprises a first electrode, a plurality of second electrodes, a first light-emitting layer sandwiched between the first electrode and a portion of the second electrodes, and a second light-emitting layer sandwiched between the first electrode and portions of the second electrodes and the first light-emitting layer. The colored filter device comprises a substrate, and a plurality of first color filter portions, a plurality of second color filter portions and a plurality of third color filter portions disposed on the surface of the substrate.

Abstract: An organic electroluminescent display panel, which comprises a substrate, at least one display structure area, at least one first dummy area, and at least one second dummy area. The display structure area comprises at least one encapsulation area, at least one pixel area, a first conducting area, a second conducting area, a wiring area, a first connecting area, and a second connecting area. The wiring area and the first dummy area connect the first connecting area, and the two conducting areas and the second dummy area connect the second connecting area. Besides, the first and the second connecting areas overlap a selected part of the encapsulation area of a neighboring display structure area. Accordingly, the number and capacity of display structure areas on the organic electroluminescent display panel are increased to obtain a uniform brightness during a lighting test.