Patents by Inventor Cheng Fan

Cheng Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240050305
    Abstract: A massage chair relates to the technical field of passive exercise equipment. It includes a seat and a driving device arranged under the seat. The driving device includes a base plate, a connecting frame, an up-and-down vibration device and a four-bar linkage device. A connecting rod is fixed on the bottom of the seat, and the connecting rod is hinged with the connecting frame. The up and down vibration device and the four-bar linkage device are set on the base plate, and the bottom of the up-and-down vibration device is connected with the connecting frame. Through the setting of the up-and-down vibration device, the bottom bracket of the massage chair can drive the massage chair to realize the overall up-and-down vibration action. Meanwhile, the four-bar linkage device ensures that the seat can be stably supported by the connecting frame, and at the same time, the four-bar linkage device can ensure that the vibration frequencies at the four fulcrum positions are consistent.
    Type: Application
    Filed: March 3, 2023
    Publication date: February 15, 2024
    Inventors: Bing Zhao, Haitang Lai, Cheng Fan, Fawen Luo
  • Publication number: 20240040769
    Abstract: A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 1, 2024
    Inventors: Chih-Wei HUANG, Hsu-Cheng FAN, En-Jui LI, Chih-Yu YEN
  • Publication number: 20240027178
    Abstract: The invention discloses a microcrack-based strain sensing element and a preparation method and use thereof. The microcrack-based strain sensing element includes a substrate layer, a metal film, a protective layer, an output electrode, and a packaging layer. The metal film is arranged on the substrate layer. The metal film is formed by deposition of two metal materials. The metal film is provided with a patterned crack structure. The protective layer is arranged on the metal film. The output electrode is connected to the metal film for outputting an electrical signal. The packaging layer is arranged on the protective layer. Compared with existing crack preparation technologies, the preparation method of the microcrack-based strain sensing element of the invention has higher-precision crack controllability, does not affect the service life of cracks, and achieves more optimized actual operation.
    Type: Application
    Filed: August 10, 2021
    Publication date: January 25, 2024
    Inventors: Qian WANG, Zezhong LU, Kejun WANG, Lei GAO, Cheng FAN, Lei ZHANG
  • Patent number: 11881446
    Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 23, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Pei Cheng Fan
  • Publication number: 20240018597
    Abstract: The present disclosure provides a method for generating a calculated cancer signature for a cancer-related phenotype based on copy number alterations (CNAs) in a patient sample. The calculated cancer signature may correspond to a somatic mutation, an mRNA expression signature, or a protein expression signature. The disclosure also provides a method treating a patient using the calculated cancer phenotype. In addition, the disclosure provides a method for generating a calculated signature based on CNAs to replicate a cancer phenotype.
    Type: Application
    Filed: October 9, 2020
    Publication date: January 18, 2024
    Inventors: Charles M. Perou, Joel S. Parker, Youli Xia, Cheng Fan
  • Publication number: 20230415461
    Abstract: Polymer film and laminated glass manufactured using the polymer film are provided. The polymer film has a first surface and a second surface, wherein the first surface has a peak material volume (Vmp) at a material ratio of 10% ranging from 0.15 ?m3/?m2 to 1.20 ?m3/?m2 and a kurtosis (Sku) ranging from 0.73 to 10.02, wherein the material ratio, peak material volume, and kurtosis are defined in accordance with ISO 25178-2:2012.
    Type: Application
    Filed: February 22, 2023
    Publication date: December 28, 2023
    Inventors: Tzu-Jung HUANG, Yen-Chen HUANG, Cheng-Fan WANG
  • Patent number: 11841551
    Abstract: An optical imaging lens includes a first lens element to a seventh lens element. The first lens element, the fifth lens element and the sixth lens element are made of plastic. The optical axis region of the image-side surface of the second lens element is convex, the optical axis region of the image-side surface of the third lens element is convex, the optical axis region of the object-side surface of the fourth lens element is convex and the optical axis region of the image-side surface of the seventh lens element is concave to satisfy (T5+G56+T6)/(G23+T3+G34+T4+G45)?1.200 by controlling the surface curvatures of each lens element to enlarge HFOV, to reduce the system length and to have good imaging quality.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: December 12, 2023
    Assignee: Genius Electronic Optical (Xiamen) Co., Ltd.
    Inventors: Ta-Cheng Fan, Jiali Lian, Qi Liu
  • Patent number: 11832435
    Abstract: A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: November 28, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Hsu-Cheng Fan, En-Jui Li, Chih-Yu Yen
  • Publication number: 20230361013
    Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.
    Type: Application
    Filed: July 3, 2023
    Publication date: November 9, 2023
    Inventor: PEI CHENG FAN
  • Publication number: 20230352549
    Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 2, 2023
    Inventors: Chih-Wei HUANG, Hsu-Cheng FAN, En-Jui LI
  • Patent number: 11764108
    Abstract: The present disclosure provides a method for preparing a semiconductor die structure with air gaps for reducing capacitive coupling between conductive features and a method for preparing the semiconductor die structure. The method includes: forming a first supporting backbone on the substrate; forming a first conductor block on the first supporting backbone; forming a second supporting backbone on the substrate; forming a second conductor block on the second supporting backbone; forming a third conductor block suspended above the substrate and connected to the first conductor block and the second conductor block; sequentially forming an energy removable layer and a capping dielectric layer over the substrate, and the energy removable layer and the capping dielectric layer separating the first conductor block, the second conductor block and the third conductor block; and performing a heat treatment process to transform the energy removable layer into a plurality of air gap structures.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: September 19, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Pei-Cheng Fan
  • Publication number: 20230288449
    Abstract: The present invention provides a battery probing module, for testing a battery defined with a contact surface having a first electrode area and a second electrode area with different polarities. The battery probing module comprises a frame and a plurality of probe units. The frame has a top plate and a bottom plate opposite to the top plate. Each of the plurality of probe units comprises a base, a first probe, and a plurality of second probes. The base is defined with a top surface and a bottom surface deflectably fixed to the top surface by a fixing unit. The first probe and the plurality of second probes protrude from the bottom surface for contacting the first electrode area and the second electrode area respectively. Wherein the first probe is within a periphery surrounded by the plurality of second probes in a vertical direction of the bottom surface.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 14, 2023
    Inventors: Shih-Ching TAN, Chun-Nan OU, Tzu-Fu CHEN, Chen-Chou WEN, Chiang-Cheng FAN
  • Publication number: 20230288673
    Abstract: An optical-lens-set includes a first lens element of a concave image-side surface near its optical-axis, a sixth lens element of negative refractive power and of a concave image-side surface near its optical-axis to go with a fifth lens element of a concave object-side surface near its optical-axis or with a seventh lens element of negative refractive power. The Abbe number ?1 of the first lens element, the Abbe number ?3 of the third lens element, the Abbe number ?4 of the fourth lens element, the Abbe number ?5 of the fifth lens element, the Abbe number ?6 of the sixth lens element and the Abbe number ?7 of the seventh lens element together satisfy 5?5?1?(?3+?4+?5+?6+?7).
    Type: Application
    Filed: March 9, 2023
    Publication date: September 14, 2023
    Applicant: Genius Electronic Optical (Xiamen) Co., Ltd.
    Inventors: Ta-Cheng Fan, Zhenfeng Xie, Yanxuan Yin
  • Patent number: 11742402
    Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: August 29, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Hsu-Cheng Fan, En-Jui Li
  • Publication number: 20230235100
    Abstract: Provided in this disclosure are zirconium and hafnium complexes that contain 1) a cyclopentadienyl ligand; 2) an adamantyl-phosphinimine ligand; and 3) at least one other ligand. The use of such a complex, in combination with an activator, as an olefin polymerization catalyst is demonstrated. The catalysts are effective for the copolymerization of ethylene with an alpha olefin (such as 1-butene, 1-hexene, or 1-octene).
    Type: Application
    Filed: April 16, 2021
    Publication date: July 27, 2023
    Applicant: NOVA CHEMICALS (INTERNATIONAL) S.A.
    Inventors: Xiaoliang Gao, Charles Carter, P. Scott Chisholm, Janelle Smiley-Wiens, Darryl Morrison, Alva Woo, Cheng Fan, Chia Yun Chang, Frederick Chiu
  • Publication number: 20230207433
    Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventor: PEI CHENG FAN
  • Publication number: 20230182447
    Abstract: The present disclosure relates to a polymer film comprising at least one first layer and at least one second layer, the first layer and the second layer each comprising a polyvinyl acetal resin and a plasticizer; wherein the polymer film has a first loss factor peak value at ?20° C. to 20° C., and a second loss factor peak value at 20° C. to 50° C.; wherein the polymer film has a loss factor valley value between the first loss factor peak value and the second loss factor peak value, the loss factor valley value is 0.15 to 0.45, and the loss factor of the polymer film at 10° C. is less than 0.5. The polymer film can still maintain good sound insulation performance at a specific ambient temperature and/or after a period of time.
    Type: Application
    Filed: June 29, 2022
    Publication date: June 15, 2023
    Inventors: Yen-Chen Huang, Tzu-Jung Huang, Cheng Fan Wang
  • Publication number: 20230187464
    Abstract: The present application discloses an optical semiconductor device. The optical semiconductor device includes a logic die including a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and including a memory cell area and a memory peripheral area, and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, and a second intra-die via positioned in the sensor peripheral area. A height of the first intra-die via is greater than a height of the second intra-die via.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Inventor: PEI CHENG FAN
  • Publication number: 20230167205
    Abstract: Provided in this disclosure are titanium complexes that contain 1) a cyclopentadienyl ligand; 2) an adamantyl-phosphinimine ligand; and 3) at least one activatable ligand. The use of such a complex, in combination with an activator, as an olefin polymerization catalyst is demonstrated. The catalysts are effective for the copolymerization of ethylene with an alpha olefin (such as 1-butene, 1-hexene or 1-octene) and enable the production of high molecular weight copolymers (Mw greater than 25,000) at high productivity under solution polymerization conditions.
    Type: Application
    Filed: April 19, 2021
    Publication date: June 1, 2023
    Applicant: NOVA Chemicals (International) S.A.
    Inventors: Xiaoliang Gao, Cheng Fan, Janelle Smiley-Wiens, Brian Molloy, P. Scott Chisholm, Charles Carter, James Goettel
  • Patent number: 11665887
    Abstract: A semiconductor structure includes a substrate, a bit line, a dielectric layer and a word line. The substrate has an active area and a trench. The bit line is on the substrate and extends along a direction. The active area includes a first portion and a second portion respectively located at two opposite sides of the bit line and spaced apart from each other along the direction. A landing area extends from the first portion of the active area to the second portion of the active area across the bit line. A dielectric layer is in the trench. The active area is surrounded by the dielectric layer. The word line is surrounded by the dielectric layer. The word line is curved and below the bit line. A portion of the word line is between first and second end portions of the landing area.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: May 30, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Hsu-Cheng Fan, Chih-Hao Kuo