Patents by Inventor Cheng-Guo Chen
Cheng-Guo Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230335630Abstract: A high-electron mobility transistor includes a substrate, a gate electrode, a drain electrode, a source electrode and a first field plate. The substrate includes an active region. The gate electrode is disposed on the substrate. The drain electrode is disposed at one side of the gate electrode. The source electrode is disposed at another side of the gate electrode. The first field plate is electrically connected with the source electrode and extends from the source electrode toward the drain electrode. An overlapping area of the first field plate and the gate electrode is smaller than an overlapping area of the gate electrode and the active region.Type: ApplicationFiled: May 11, 2022Publication date: October 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jian-Li Lin, Cheng-Guo Chen, Ta-Kang Lo, Cheng-Han Wu
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Publication number: 20230048684Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.Type: ApplicationFiled: October 31, 2022Publication date: February 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
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Publication number: 20220181505Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.Type: ApplicationFiled: January 11, 2021Publication date: June 9, 2022Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
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Patent number: 10707305Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.Type: GrantFiled: March 14, 2019Date of Patent: July 7, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
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Publication number: 20190214463Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.Type: ApplicationFiled: March 14, 2019Publication date: July 11, 2019Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
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Patent number: 10276663Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.Type: GrantFiled: July 18, 2016Date of Patent: April 30, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
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Publication number: 20180122705Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.Type: ApplicationFiled: November 2, 2016Publication date: May 3, 2018Inventors: Tai-You Chen, Cheng-Guo Chen, Kun-Yuan Wu, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo, Shang-Jr Chen
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Patent number: 9960083Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.Type: GrantFiled: November 2, 2016Date of Patent: May 1, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tai-You Chen, Cheng-Guo Chen, Kun-Yuan Wu, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo, Shang-Jr Chen
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Publication number: 20180019341Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.Type: ApplicationFiled: July 18, 2016Publication date: January 18, 2018Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
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Patent number: 9384962Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.Type: GrantFiled: April 7, 2011Date of Patent: July 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
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Patent number: 9318609Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.Type: GrantFiled: February 12, 2015Date of Patent: April 19, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Cheng-Guo Chen, Chien-Ting Lin
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Patent number: 9312352Abstract: A method for fabricating a field-effect transistor is provided. The method includes: forming a gate dielectric layer and a barrier layer on a substrate in sequence; forming a first silicon layer on and in contact with the barrier layer; performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer; and forming a second silicon layer on and in contact with the first silicon layer.Type: GrantFiled: October 2, 2015Date of Patent: April 12, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kun-Yuan Lo, Chih-Wei Yang, Cheng-Guo Chen, Rai-Min Huang, Jian-Cun Ke
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Publication number: 20160027885Abstract: A method for fabricating a field-effect transistor is provided. The method includes: forming a gate dielectric layer and a barrier layer on a substrate in sequence; forming a first silicon layer on and in contact with the barrier layer; performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer; and forming a second silicon layer on and in contact with the first silicon layer.Type: ApplicationFiled: October 2, 2015Publication date: January 28, 2016Inventors: Kun-Yuan LO, Chih-Wei YANG, Cheng-Guo CHEN, Rai-Min HUANG, Jian-Cun KE
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Publication number: 20150380506Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.Type: ApplicationFiled: September 3, 2015Publication date: December 31, 2015Inventors: Jun-Jie Wang, Po-Chao Tsao, Chia-Jui Liang, Shih-Fang Tzou, Chien-Ting Lin, Cheng-Guo Chen, Ssu-I Fu, Yu-Hsiang Hung, Chung-Fu Chang
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Patent number: 9184254Abstract: A field-effect transistor comprises a substrate, a gate dielectric layer, a barrier layer, a metal gate electrode and a source/drain structure. The gate dielectric layer is disposed on the substrate. The barrier layer having a titanium-rich surface is disposed on the gate dielectric layer. The metal gate electrode is disposed on the titanium-diffused surface. The source/drain structure is formed in the substrate and adjacent to the metal gate electrode.Type: GrantFiled: May 2, 2013Date of Patent: November 10, 2015Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kun-Yuan Lo, Chih-Wei Yang, Cheng-Guo Chen, Rai-Min Huang, Jian-Cun Ke
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Patent number: 9159798Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.Type: GrantFiled: May 3, 2013Date of Patent: October 13, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jun-Jie Wang, Po-Chao Tsao, Chia-Jui Liang, Shih-Fang Tzou, Chien-Ting Lin, Cheng-Guo Chen, Ssu-I Fu, Yu-Hsiang Hung, Chung-Fu Chang
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Patent number: 9070710Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.Type: GrantFiled: June 7, 2013Date of Patent: June 30, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ssu-I Fu, Cheng-Guo Chen, Yu-Hsiang Hung, Chung-Fu Chang, Chien-Ting Lin
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Publication number: 20150155386Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.Type: ApplicationFiled: February 12, 2015Publication date: June 4, 2015Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Cheng-Guo Chen, Chien-Ting Lin
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Patent number: 8993384Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.Type: GrantFiled: June 9, 2013Date of Patent: March 31, 2015Assignee: United Microelectronics Corp.Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Cheng-Guo Chen, Chien-Ting Lin
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Patent number: 8981487Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.Type: GrantFiled: July 31, 2013Date of Patent: March 17, 2015Assignee: United Microelectronics Corp.Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chien-Ting Lin, Po-Chao Tsao, Chung-Fu Chang, Cheng-Guo Chen