Patents by Inventor Cheng-Han Wu

Cheng-Han Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10475768
    Abstract: An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10459736
    Abstract: An electronic device includes a display and a processor. The display displays a present application program in a first brightness. When the electronic device in normal-use status receives no user input for a predetermined idle time period, the processor determines whether the present application program is in a half-suspend list. If yes, the processor controls the electronic device to enter a half-suspend status and keep the present application program running, but controls the display to display the present application program in a second brightness, which is less bright than the first brightness. A half-suspend controlling method of the electronic device is also provided.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 29, 2019
    Assignee: Chiun Mai Communication Systensms, Inc.
    Inventor: Cheng-Han Wu
  • Publication number: 20190295955
    Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20190245061
    Abstract: Methods of semiconductor arrangement formation are provided. A method of forming the semiconductor arrangement includes forming a first nucleus on a substrate in a trench or between dielectric pillars on the substrate. Forming the first nucleus includes applying a first source material beam at a first angle relative to a top surface of the substrate and concurrently applying a second source material beam at a second angle relative to the top surface of the substrate. A first semiconductor column is formed from the first nucleus by rotating the substrate while applying the first source material beam and the second source material beam. Forming the first semiconductor column in the trench or between the dielectric pillars using the first source material beam and the second source material beam restricts the formation of the first semiconductor column to a single direction.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Inventors: Wei-Chieh CHEN, Hao-Hsiung LIN, Shu-Han CHEN, You-Ru LIN, Cheng-Hsien WU, Chih-Hsin KO, Clement Hsingjen WANN
  • Patent number: 10353569
    Abstract: A crop frame adjusting method includes displaying an image; displaying a crop frame on the image; and in response to touches within a virtual frame corresponding to the crop frame are detected, resizing the crop frame according to movements of the touches, wherein the virtual frame is extended from the crop frame.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: July 16, 2019
    Assignee: HTC Corporation
    Inventors: Cheng-Hsun Lu, Yi-Ting Hou, Ke-Neng Wu, Chieh-Hua Kuo, Wei-Han Wu
  • Publication number: 20190187023
    Abstract: A gentle start-up device includes: a rotational type hollow pipe body, including an inlet and an outlet, and having an inner wall provided with a plurality of bar-shaped fins; a transmission unit, physically connected to the rotational type hollow pipe body; and a driving unit, physically connected to the transmission unit for driving the transmission unit to rotate the rotational type hollow pipe body in a rotational direction and to achieve a predetermined rotational speed according to a water supply flow value of a water turbine of a hydraulic generator set, whereby water flow which passes through the rotational type hollow pipe body generates rotational flow.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: BO-HAN WANG, Cheng-En Wu, Ren-Yo Huang
  • Patent number: 10319681
    Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20190164745
    Abstract: A method includes depositing a target layer over a substrate; reducing a reflection of a light incident upon the target layer by implanting ions into the target layer, resulting in an ion-implanted target layer; coating a photoresist layer over the ion-implanted target layer; exposing the photoresist layer to the light using a photolithography process, wherein the target layer reduces reflection of the light at an interface between the ion-implanted target layer and the photoresist layer during the photolithography process; developing the photoresist layer to form a resist pattern; etching the ion-implanted target layer with the resist pattern as an etch mask; processing the substrate using at least the etched ion-implanted target layer as a process mask; and removing the etched ion-implanted target layer.
    Type: Application
    Filed: October 31, 2018
    Publication date: May 30, 2019
    Inventors: Cheng-Han Yang, Tsung-Han Wu, Chih-Wei Chang, Hsin-mei Lin, I-Chun Hsieh, Hsi-Yen Chang
  • Publication number: 20190156587
    Abstract: A digital dental mesh segmentation method and a digital dental mesh segmentation device are provided. The digital dental mesh segmentation method includes: receiving a digital dental mesh, including a plurality of teeth; inserting a tooth interface separator at a tooth interface of the digital dental mesh, the tooth interface separator being at a first location; receiving a three-dimensional movement signal and a three-dimensional rotation signal to move and rotate the tooth interface separator from the first location to a second location; and segmenting the digital dental mesh according to the tooth interface separator at the second location to obtain an independent digital teeth model.
    Type: Application
    Filed: November 23, 2018
    Publication date: May 23, 2019
    Applicant: Candor Ltd.
    Inventors: Chien-Chih Huang, Cheng-Han Wu, Wen-Pin Hsu, Ting-Hui Kao, Chih-Hao Hsu, Hsuan-Hung Liu, Jen-How Wang, Chi-Kang Chen
  • Publication number: 20190157073
    Abstract: Methods for forming a semiconductor structure including using a photoresist material are provided. The method for forming a semiconductor structure includes forming a material layer over a substrate and forming a photoresist layer over the material layer. The method for forming a semiconductor structure further includes performing an exposure process on the photoresist layer and developing the photoresist layer. In addition, the photoresist layer is made of a photoresist material comprising a photosensitive polymer, and the photosensitive polymer has a first photosensitive functional group bonding to a main chain of the photosensitive polymer and a first acid labile group bonding to the first photosensitive functional group.
    Type: Application
    Filed: September 6, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hui WENG, Cheng-Han WU, Ching-Yu CHANG, Chin-Hsiang LIN, Siao-Shan WANG
  • Patent number: 10290584
    Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20190139837
    Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate including a multi-voltage device region. A first pair of source/drain regions are spaced apart from one another by a first channel region. A dielectric layer is disposed over the first channel region. A barrier layer is disposed over the dielectric layer. A fully silicided gate is disposed over the first channel region and is vertically separated from the semiconductor substrate by a work function tuning layer. The work function tuning layer separates the fully silicided gate from the barrier layer.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 9, 2019
    Inventors: Chun-Han Tsao, Chii-Ming Wu, Cheng-Yuan Tsai, Yi-Huan Chen
  • Publication number: 20190122940
    Abstract: A device includes a semiconductor fin, a first source/drain feature, a second source/drain feature, and a dielectric plug. The first source/drain feature adjoins the semiconductor fin. The second source/drain feature adjoins the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin, the dielectric plug is between the first source/drain feature and the second source/drain feature. The dielectric plug includes a waist and a first portion below the waist, and a width of the waist is less than a width of the first portion of the dielectric plug.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Kuei-Ming CHANG, Rei-Jay HSIEH, Cheng-Han WU, Chie-Iuan LIN
  • Publication number: 20190103306
    Abstract: A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.
    Type: Application
    Filed: June 13, 2018
    Publication date: April 4, 2019
    Inventors: Tzu-Yang LIN, Cheng-Han WU, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20190053732
    Abstract: An attraction-attachable electrically conductive pad includes a conductive film and at least one attaching film. The at least one attaching film is coupled to the conductive film and has a surface on which a plurality of miniature structures in the form of projections are formed such that the conductive film is attachable to a human skin through an attractive force of positive and negative charges between molecules of the projections. As such, in use, the arrangement of being attachable to a human skin through an attractive force of positive and negative charges between molecules of the projections helps prevent positional shifting of the conductive film during a detection operation and helps keep in a state of contacting a body surface, and helps keep comfortable and air ventilating for long term wear in order to achieve effective detection of physiological signals.
    Type: Application
    Filed: August 15, 2017
    Publication date: February 21, 2019
    Applicant: KING'S METAL FIBER TECHNOLOGIES CO., LTD.
    Inventors: Cheng Han WU, Reng Sho CHEN, Hong Hsu HUANG
  • Publication number: 20190004430
    Abstract: The present disclosure provides lithography resist materials and corresponding lithography techniques for improving lithography resolution, in particular, by reducing swelling of resist layers during development. An exemplary lithography method includes performing a treatment process on a resist layer to cause cross-linking of acid labile group components of the resist layer via cross-linkable functional components, performing an exposure process on the resist layer, and performing a development process on the resist layer. In some implementations, the resist layer includes an exposed portion and an unexposed portion after the exposure process, and the treatment process reduces solubility of the unexposed portion to a developer used during the development process by increasing a molecular weight of a polymer in the unexposed portion. The treatment process is performed before or after the exposure process.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: Ming-Hui Weng, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10157800
    Abstract: A semiconductor device includes a substrate, a first source/drain feature, a second source/drain feature and a dielectric plug. The substrate has a semiconductor fin. The first source/drain feature is embedded in the semiconductor fin. The second source/drain feature is embedded in the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin. The dielectric plug is in between the first source/drain feature and the second source/drain feature. The dielectric plug is separated from the first source/drain feature and the second source/drain feature.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuei-Ming Chang, Rei-Jay Hsieh, Cheng-Han Wu, Chie-Iuan Lin
  • Publication number: 20180348639
    Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a resist layer over a substrate and performing an exposing process to the resist layer. The resist layer includes a polymer backbone, an acid labile group (ALG) bonded to the polymer backbone, a sensitizer bonded to the polymer backbone, a photo-acid generator (PAG), and a thermo-base generator (TBG). The method further includes baking the resist layer at a first temperature and subsequently at a second temperature. The second temperature is higher than the first temperature. The method further includes developing the resist layer in a developer, thereby forming a patterned resist layer.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 6, 2018
    Inventors: Chen-Yu Liu, Ya-Ching Chang, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20180337036
    Abstract: The present disclosure provides a method for planarization. The method includes providing a substrate having a top surface and a trench recessed from the top surface; coating a sensitive material layer on the top surface of the substrate, wherein the sensitive material layer fills in the trench; performing an activation treatment to the sensitive material layer so that portions of the material layer are chemically changed; and performing a wet chemical process to the sensitive material layer so that top portions of the sensitive material layer above the trench are removed, wherein remaining portions of the sensitive material layer have top surfaces substantially coplanar with the top surface of the substrate.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 22, 2018
    Inventors: Ming-Hui Weng, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20180308769
    Abstract: A semiconductor device includes a substrate, a first source/drain feature, a second source/drain feature and a dielectric plug. The substrate has a semiconductor fin. The first source/drain feature is embedded in the semiconductor fin. The second source/drain feature is embedded in the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin. The dielectric plug is in between the first source/drain feature and the second source/drain feature. The dielectric plug is separated from the first source/drain feature and the second source/drain feature.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 25, 2018
    Inventors: Kuei-Ming CHANG, Rei-Jay HSIEH, Cheng-Han WU, Chie-Iuan LIN