Patents by Inventor CHENG HAO
CHENG HAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12376364Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.Type: GrantFiled: July 28, 2022Date of Patent: July 29, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Wei Hsu, Pei Ying Lai, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
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Publication number: 20250234568Abstract: Structures of a semiconductor device structure are provided. The semiconductor device structure includes a first insulating layer formed over a semiconductor substrate and an interconnect structure formed in the first insulating layer. The semiconductor device structure also includes a second insulating layer formed over the first insulating layer and a capacitor device embedded in the second insulating layer. The capacitor device includes a first capacitor electrode layer electrically connected to the interconnect structure, a capacitor insulating stack formed over the first capacitor electrode layer and a second capacitor electrode layer formed over the capacitor insulating stack. The capacitor insulating stack includes first layers alternatingly stacked with second layers.Type: ApplicationFiled: March 31, 2025Publication date: July 17, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-En JENG, Hsiang-Ku SHEN, Cheng-Hao HOU, Chen-Chiu HUANG, Dian-Hau CHEN
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Publication number: 20250226249Abstract: The present disclosure provides a system and method for determining condition of wafers during processing of the wafers. The system and method include detecting vibrations of a wafer transfer robot, generating signals based upon the vibrations, and processing the signals for determining a condition of the wafers held by the wafer transfer robot.Type: ApplicationFiled: March 25, 2025Publication date: July 10, 2025Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Sung HUNG, Chia-Lun CHEN, Cheng-Hao KUO
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Patent number: 12354810Abstract: A wound capacitor package structure includes a wound assembly, a conductive assembly, a package assembly, a bottom seat plate and a pin protection assembly. The conductive assembly includes a first and a second conductive pin. The package assembly is configured for enclosing the wound assembly. The bottom seat plate is disposed on a bottom side of the package assembly. The pin protection assembly includes a first pin protection layer configured to partially cover the first conductive pin, and a second pin protection layer configured to partially cover the second conductive pin. The first conductive pin includes a first exposed portion exposed outside the package assembly, and the second conductive pin includes a second exposed portion exposed outside the package assembly. The first and the second pin protection layer are disposed on the first and the second exposed portion for protecting the first and the second conductive pin, respectively.Type: GrantFiled: February 17, 2023Date of Patent: July 8, 2025Assignee: APAQ TECHNOLOGY CO., LTD.Inventors: Chieh Lin, Chung-Jui Su, Cheng-Hao Lu
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Publication number: 20250215592Abstract: An electrolyzer includes a casing and an electrolytic device. The casing includes two side plates. The electrolytic device is disposed between the two side plates, and the electrolytic device includes a plurality of porous layers, a plurality of current collector plates, a plurality of membranes and a plurality of heating units. The current collector plates are arranged in an alternating manner with the porous layers. The membranes are disposed corresponding to the porous layers. The heating units are respectively disposed on at least some of the current collector plates.Type: ApplicationFiled: December 6, 2024Publication date: July 3, 2025Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Po-Jen SU, Wen-Sheng CHANG, Chia-Hsin LEE, Cheng-Hao YANG, Chia-Hao CHEN
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Publication number: 20250215064Abstract: A novel fusion protein to overcome the current difficulties related to application of monoclonal antibodies in disease treatment and in other fields, particularly those requiring ADCC, e.g. for depletion of tumor cells, virally-infected cells, or immune-modulating cells, etc. One example of the fusion protein is an extracellular domain of a high-affinity variant of human CD 16 A fused to an anti-CD3 antibody or its antigen-binding fragment thereof that specifically binds to an epitope on human CD3 or a fragment thereof.Type: ApplicationFiled: January 18, 2025Publication date: July 3, 2025Applicant: MANYSMART THERAPEUTICS, INC.Inventors: HSIN-YI HUANG, CHENG HAO LIAO, CHUN-MING LIN
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Patent number: 12328365Abstract: The present invention provides a chip including a plurality of application circuits and a UART interface. The plurality of application circuits, configured to generate a plurality of data, respectively, wherein the plurality of data respectively generated by the plurality of application circuits are transmitted to another chip via the same UART interface.Type: GrantFiled: July 13, 2023Date of Patent: June 10, 2025Assignee: MEDIATEK INC.Inventors: Chia-Hung Hsu, Cheng-Hao Yao, Jyun-Ji Wang, Yu-Lin Tsai
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Publication number: 20250135331Abstract: Dual-function input devices for a computing device may include a housing and an actuator disposed within the housing. The actuator may be pivotable relative to the housing in a first direction and a second direction. The actuator may include a first connector and a second connector. The input devices may include an input lever that is coupleable with the actuator via one of the first connector and the second connector. The actuator may be configurable between a first mode by coupling the input lever with the first connector and a second mode by coupling the input lever with the second connector. In the first mode the input lever and the actuator may be pivotable in the first direction by a first distance. In the second mode the input lever and the actuator may be pivotable in the first direction by a second distance that is greater than the first distance.Type: ApplicationFiled: October 30, 2023Publication date: May 1, 2025Inventors: David Maher, Andrew Kelly, Simon Baumgartner, Cheng Hao Chiu, Baptiste Merminod
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Patent number: 12288703Abstract: The present disclosure provides a system and method for determining condition of wafers during processing of the wafers. The system and method include detecting vibrations of a wafer transfer robot, generating signals based upon the vibrations, and processing the signals for determining a condition of the wafers held by the wafer transfer robot.Type: GrantFiled: August 4, 2023Date of Patent: April 29, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Sung Hung, Chia-Lun Chen, Cheng-Hao Kuo
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Publication number: 20250133800Abstract: A semiconductor device includes a MEOL structure and a BEOL structure. The BEOL structure is formed over the MEOL structure and includes a first dielectric layer, a spacer and a conductive portion. The first dielectric layer has a lateral surface and a recess, wherein the recess is recessed with respect to the lateral surface. The spacer is formed the lateral surface and covers an opening of the recess. The conductive portion is formed adjacent to the spacer.Type: ApplicationFiled: October 18, 2023Publication date: April 24, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Chih-Wei LU, Cheng-Hao CHEN
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Publication number: 20250133759Abstract: A method forming a source/drain region based on a first portion of a semiconductor region, forming a high-k dielectric layer based on a second portion of the semiconductor region, forming a dipole film on the high-k dielectric layer, performing a treatment process on the dipole film using a process gas comprising nitrogen and hydrogen, performing a drive-in process to drive a dipole dopant in the dipole film into the high-k dielectric layer, and depositing a work-function layer on the high-k dielectric layer.Type: ApplicationFiled: January 23, 2024Publication date: April 24, 2025Inventors: Chun-Hsiu Chiang, Pei Ying Lai, Cheng-Hao Hou, Chi On Chui, Shan-Mei Liao, Hung-Chi Wu
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Publication number: 20250118656Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first conductive line, a first conductive via, a second conductive line, and a first barrier layer. The first conductive line is disposed on the substrate. The first conductive via is disposed on the first conductive line. The second conductive line is disposed on the first conductive line. The first barrier layer is disposed between the first conductive via and the second conductive line.Type: ApplicationFiled: October 6, 2023Publication date: April 10, 2025Inventors: HWEI-JAY CHU, HSI-WEN TIEN, WEI-HAO LIAO, YU-TENG DAI, HSIN-CHIEH YAO, CHENG-HAO CHEN, CHIH WEI LU
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Patent number: 12272735Abstract: In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.Type: GrantFiled: March 4, 2022Date of Patent: April 8, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hao Hou, Che-Hao Chang, Da-Yuan Lee, Chi On Chui
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Patent number: 12269863Abstract: A novel fusion protein to overcome the current difficulties related to application of monoclonal antibodies in disease treatment and in other fields, particularly those requiring ADCC, e.g. for depletion of tumor cells, virally-infected cells, or immune-modulating cells, etc. One example of the fusion protein is an extracellular domain of a high-affinity variant of human CD 16 A fused to an anti-CD3 antibody or its antigen-binding fragment thereof that specifically binds to an epitope on human CD3 or a fragment thereof.Type: GrantFiled: May 23, 2019Date of Patent: April 8, 2025Assignee: MANYSMART THERAPEUTICS, INC.Inventors: Hsin-Yi Huang, Cheng Hao Liao, Chun-Ming Lin
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Patent number: 12266681Abstract: Structures of a semiconductor device structure are provided. The semiconductor device structure includes a first insulating layer formed over a semiconductor substrate and an interconnect structure formed in the first insulating layer. The semiconductor device structure also includes a second insulating layer formed over the first insulating layer and a capacitor device embedded in the second insulating layer. The capacitor device includes a first capacitor electrode layer electrically connected to the interconnect structure, a capacitor insulating stack formed over the first capacitor electrode layer and a second capacitor electrode layer formed over the capacitor insulating stack. The capacitor insulating stack includes first layers alternatingly stacked with second layers. The dielectric constant of the first layer is different than the dielectric constant of the second layer.Type: GrantFiled: January 5, 2022Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-En Jeng, Hsiang-Ku Shen, Cheng-Hao Hou, Chen-Chiu Huang, Dian-Hau Chen
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Publication number: 20250098346Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.Type: ApplicationFiled: January 19, 2024Publication date: March 20, 2025Inventors: Wen-Chung Chen, Chia-Yu Wei, Kuo-Cheng Lee, Cheng-Hao Chiu, Hsiu Chi Yu, Hsun-Ying Huang, Ming-Hong Su
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Publication number: 20250096192Abstract: A package structure is provided, in which a second electronic element having a plurality of conductive bumps is stacked on a first electronic element arranged with a positioning layer. The plurality of conductive bumps are inserted into a plurality of positioning holes of the positioning layer, and the second electronic element is bonded onto the positioning layer and electrically connected to the first electronic element via the plurality of conductive bumps, such that the hybrid bonding technology is replaced via the arrangement of the positioning holes and the conductive bumps, thereby reducing packaging costs.Type: ApplicationFiled: June 12, 2024Publication date: March 20, 2025Inventors: Ghang-Chun LAI, Meng-Huang SIE, Cheng-Hao HEH, Ming-Chin HSU
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Publication number: 20250089277Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing forming a first metal-insulator-metal (MIM) capacitor over a substrate and forming a second MIM capacitor over the first MIM capacitor. The forming of the first MIM capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-K dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-K dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.Type: ApplicationFiled: November 30, 2023Publication date: March 13, 2025Inventors: Chia-Yueh Chou, Hsiang-Ku Shen, Chen-Chiu Huang, Dian-Hau Chen, Cheng-Hao Hou, Kun-Yu Lee, Ming-Ho Lin, Alvin Universe Tang, Chun-Hsiu Chiang
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Publication number: 20250079270Abstract: A power management integrated circuit (PMIC) soldered onto a printed circuit board, includes: a first output stage circuit and a second output stage circuit. In a separate power supply configuration, first and second current inflow pins of the first and second output stage circuits are soldered to first and second current inflow printed lines, respectively, wherein the first and second current inflow printed lines are not directly electrically connected to each other; and, first and second current outflow pins of the first and second output stage circuits are soldered to first and second current outflow printed lines respectively, wherein the first and second current outflow printed lines are not directly electrically connected to each other. In a cooperation power supply configuration, the first and second current inflow pins are both soldered to a common current inflow printed line of the PCB, to be electrically connected with each other.Type: ApplicationFiled: January 11, 2024Publication date: March 6, 2025Inventors: Cheng-Han Lin, Chan-Chuan Li, Bo-Zhou Ke, Chun-Yao Huang, Cheng-Hao Tseng
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Patent number: D1087105Type: GrantFiled: January 31, 2025Date of Patent: August 5, 2025Assignee: Logitech Europe S.A.Inventors: Matthew Pugmire, Cheng Hao Chiu, Ping Hao Chang, Davin O'Mahony