Patents by Inventor CHENG HAO

CHENG HAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250135331
    Abstract: Dual-function input devices for a computing device may include a housing and an actuator disposed within the housing. The actuator may be pivotable relative to the housing in a first direction and a second direction. The actuator may include a first connector and a second connector. The input devices may include an input lever that is coupleable with the actuator via one of the first connector and the second connector. The actuator may be configurable between a first mode by coupling the input lever with the first connector and a second mode by coupling the input lever with the second connector. In the first mode the input lever and the actuator may be pivotable in the first direction by a first distance. In the second mode the input lever and the actuator may be pivotable in the first direction by a second distance that is greater than the first distance.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 1, 2025
    Inventors: David Maher, Andrew Kelly, Simon Baumgartner, Cheng Hao Chiu, Baptiste Merminod
  • Patent number: 12288703
    Abstract: The present disclosure provides a system and method for determining condition of wafers during processing of the wafers. The system and method include detecting vibrations of a wafer transfer robot, generating signals based upon the vibrations, and processing the signals for determining a condition of the wafers held by the wafer transfer robot.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Sung Hung, Chia-Lun Chen, Cheng-Hao Kuo
  • Publication number: 20250133759
    Abstract: A method forming a source/drain region based on a first portion of a semiconductor region, forming a high-k dielectric layer based on a second portion of the semiconductor region, forming a dipole film on the high-k dielectric layer, performing a treatment process on the dipole film using a process gas comprising nitrogen and hydrogen, performing a drive-in process to drive a dipole dopant in the dipole film into the high-k dielectric layer, and depositing a work-function layer on the high-k dielectric layer.
    Type: Application
    Filed: January 23, 2024
    Publication date: April 24, 2025
    Inventors: Chun-Hsiu Chiang, Pei Ying Lai, Cheng-Hao Hou, Chi On Chui, Shan-Mei Liao, Hung-Chi Wu
  • Publication number: 20250133800
    Abstract: A semiconductor device includes a MEOL structure and a BEOL structure. The BEOL structure is formed over the MEOL structure and includes a first dielectric layer, a spacer and a conductive portion. The first dielectric layer has a lateral surface and a recess, wherein the recess is recessed with respect to the lateral surface. The spacer is formed the lateral surface and covers an opening of the recess. The conductive portion is formed adjacent to the spacer.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Chih-Wei LU, Cheng-Hao CHEN
  • Publication number: 20250118656
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first conductive line, a first conductive via, a second conductive line, and a first barrier layer. The first conductive line is disposed on the substrate. The first conductive via is disposed on the first conductive line. The second conductive line is disposed on the first conductive line. The first barrier layer is disposed between the first conductive via and the second conductive line.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: HWEI-JAY CHU, HSI-WEN TIEN, WEI-HAO LIAO, YU-TENG DAI, HSIN-CHIEH YAO, CHENG-HAO CHEN, CHIH WEI LU
  • Patent number: 12272735
    Abstract: In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hao Hou, Che-Hao Chang, Da-Yuan Lee, Chi On Chui
  • Patent number: 12269863
    Abstract: A novel fusion protein to overcome the current difficulties related to application of monoclonal antibodies in disease treatment and in other fields, particularly those requiring ADCC, e.g. for depletion of tumor cells, virally-infected cells, or immune-modulating cells, etc. One example of the fusion protein is an extracellular domain of a high-affinity variant of human CD 16 A fused to an anti-CD3 antibody or its antigen-binding fragment thereof that specifically binds to an epitope on human CD3 or a fragment thereof.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: April 8, 2025
    Assignee: MANYSMART THERAPEUTICS, INC.
    Inventors: Hsin-Yi Huang, Cheng Hao Liao, Chun-Ming Lin
  • Patent number: 12266681
    Abstract: Structures of a semiconductor device structure are provided. The semiconductor device structure includes a first insulating layer formed over a semiconductor substrate and an interconnect structure formed in the first insulating layer. The semiconductor device structure also includes a second insulating layer formed over the first insulating layer and a capacitor device embedded in the second insulating layer. The capacitor device includes a first capacitor electrode layer electrically connected to the interconnect structure, a capacitor insulating stack formed over the first capacitor electrode layer and a second capacitor electrode layer formed over the capacitor insulating stack. The capacitor insulating stack includes first layers alternatingly stacked with second layers. The dielectric constant of the first layer is different than the dielectric constant of the second layer.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-En Jeng, Hsiang-Ku Shen, Cheng-Hao Hou, Chen-Chiu Huang, Dian-Hau Chen
  • Publication number: 20250096192
    Abstract: A package structure is provided, in which a second electronic element having a plurality of conductive bumps is stacked on a first electronic element arranged with a positioning layer. The plurality of conductive bumps are inserted into a plurality of positioning holes of the positioning layer, and the second electronic element is bonded onto the positioning layer and electrically connected to the first electronic element via the plurality of conductive bumps, such that the hybrid bonding technology is replaced via the arrangement of the positioning holes and the conductive bumps, thereby reducing packaging costs.
    Type: Application
    Filed: June 12, 2024
    Publication date: March 20, 2025
    Inventors: Ghang-Chun LAI, Meng-Huang SIE, Cheng-Hao HEH, Ming-Chin HSU
  • Publication number: 20250098346
    Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.
    Type: Application
    Filed: January 19, 2024
    Publication date: March 20, 2025
    Inventors: Wen-Chung Chen, Chia-Yu Wei, Kuo-Cheng Lee, Cheng-Hao Chiu, Hsiu Chi Yu, Hsun-Ying Huang, Ming-Hong Su
  • Publication number: 20250089277
    Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing forming a first metal-insulator-metal (MIM) capacitor over a substrate and forming a second MIM capacitor over the first MIM capacitor. The forming of the first MIM capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-K dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-K dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 13, 2025
    Inventors: Chia-Yueh Chou, Hsiang-Ku Shen, Chen-Chiu Huang, Dian-Hau Chen, Cheng-Hao Hou, Kun-Yu Lee, Ming-Ho Lin, Alvin Universe Tang, Chun-Hsiu Chiang
  • Publication number: 20250079270
    Abstract: A power management integrated circuit (PMIC) soldered onto a printed circuit board, includes: a first output stage circuit and a second output stage circuit. In a separate power supply configuration, first and second current inflow pins of the first and second output stage circuits are soldered to first and second current inflow printed lines, respectively, wherein the first and second current inflow printed lines are not directly electrically connected to each other; and, first and second current outflow pins of the first and second output stage circuits are soldered to first and second current outflow printed lines respectively, wherein the first and second current outflow printed lines are not directly electrically connected to each other. In a cooperation power supply configuration, the first and second current inflow pins are both soldered to a common current inflow printed line of the PCB, to be electrically connected with each other.
    Type: Application
    Filed: January 11, 2024
    Publication date: March 6, 2025
    Inventors: Cheng-Han Lin, Chan-Chuan Li, Bo-Zhou Ke, Chun-Yao Huang, Cheng-Hao Tseng
  • Patent number: 12244214
    Abstract: An AC-DC conversion circuit provides a three-phase power source. The AC-DC conversion circuit includes a first inductor, a second inductor, a third inductor, a switch bridge arm assembly, and a control unit. The switch bridge arm assembly includes three switch bridge arms, and each switch bridge arm includes an upper switch and a lower switch. A plurality of common-connected nodes between the upper switches and the lower switches are coupled to the three-phase power source through the first inductor, the second inductor, and the third inductor. The control unit turns on the upper switch and the lower switch to provide a current detection loop. The control unit acquires a magnitude of a first current flowing through the first inductor and a magnitude of a third current flowing through the third inductor, and determines whether a current detection mechanism of the first current and the third current is normal.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: March 4, 2025
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Cheng-Te Li, Nian-Ci Chen, Chih-Yuan Chuang, Cheng-Hao Hsueh
  • Patent number: 12235586
    Abstract: Impurities in a liquefied solid fuel utilized in a droplet generator of an extreme ultraviolet photolithography system are removed from vessels containing the liquefied solid fuel. Removal of the impurities increases the stability and predictability of droplet formation which positively impacts wafer yield and droplet generator lifetime.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hao Lai, Ming-Hsun Tsai, Hsin-Feng Chen, Wei-Shin Cheng, Yu-Kuang Sun, Cheng-Hsuan Wu, Yu-Fa Lo, Shih-Yu Tu, Jou-Hsuan Lu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Patent number: 12225148
    Abstract: A communication device includes a wireless communication module, a frame element, and a fixing assembly. The frame element includes a bottom plate and a side plate connected to the bottom plate, and the side plate includes a fixing hole. The fixing assembly includes a first fixing element. The first fixing element includes a first connection portion and a first fixing portion. The first connection portion is adapted to be fixed to the wireless communication module, and the first fixing portion includes a first neck portion and a first protruding portion. The first neck portion is adapted to be in the fixing hole, and the first neck portion is connected between the first connection portion and the first protruding portion. Hence, the fixing component fixes the wireless communication module with the frame element.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: February 11, 2025
    Assignee: WISTRON CORPORATION
    Inventors: Cheng-Hao Wu, Wei-Hsiang Huang, Pin-Shiuan Wang
  • Publication number: 20240429156
    Abstract: A device includes a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. The second dielectric layer and the first dielectric layer have different material compositions. A metal-insulator-metal (MIM) structure is embedded in the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer. The third dielectric layer and the second dielectric layer have different material compositions. The first dielectric layer or the third dielectric layer may contain silicon nitride (SiN), the second dielectric layer may contain silicon oxide (SiO2).
    Type: Application
    Filed: June 20, 2023
    Publication date: December 26, 2024
    Inventors: Chia-Yueh Chou, Hsiang-Ku Shen, Li-Chung Yu, Wen-Ling Chang, Chen-Chiu Huang, Dian-Hau Chen, Cheng-Hao Hou, Shin-Hung Tsai, Alvin Universe Tang, Kun-Yu Lee, Chun-Hsiu Chiang
  • Publication number: 20240421065
    Abstract: A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices, and a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In some embodiments, the MIM capacitor structure includes a first conductor plate layer, an insulator layer on the first conductor plate layer, and a second conductor plate layer on the insulator layer. In some examples, the insulator layer includes a metal oxide sandwich structure.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 19, 2024
    Inventors: Chia-Yueh CHOU, Wen-Tzu CHEN, Wen-Ling CHANG, Hsiang-Ku SHEN, Alvin Universe TANG, Chun-Hsiu CHIANG, Shin-Hung TSAI, Kun-Yu LEE, Cheng-Hao HOU, Dian-Hau CHEN, Li-Chung YU
  • Publication number: 20240413221
    Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.
    Type: Application
    Filed: July 11, 2024
    Publication date: December 12, 2024
    Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen
  • Patent number: 12167526
    Abstract: An extreme ultraviolet (EUV) photolithography system generates EUV light by irradiating droplets with a laser. The system includes a droplet generator with a nozzle and a piezoelectric structure coupled to the nozzle. The generator outputs groups of droplets. A control system applies a voltage waveform to the piezoelectric structure while the nozzle outputs the group of droplets. The waveform causes the droplets of the group to have a spread of velocities that results in the droplets coalescing into a single droplet prior to being irradiated by the laser.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Kuang Sun, Cheng-Hao Lai, Yu-Huan Chen, Wei-Shin Cheng, Ming-Hsun Tsai, Hsin-Feng Chen, Chiao-Hua Cheng, Cheng-Hsuan Wu, Yu-Fa Lo, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Patent number: D1055942
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: December 31, 2024
    Assignee: Logitech Europe S.A.
    Inventors: Matthew Pugmire, Cheng Hao Chiu, Ping Hao Chang, Davin O'Mahony