Abstract: In fabricating a lateral metal oxide semiconductor (MOS) device, source and drain regions are formed in a base semiconductor. A gate oxide layer is disposed on the base semiconductor, and a gate layer on the gate oxide layer. Photolithographically patterned etching of the gate layer forms a first side of the gate facing the source. Photolithographically patterned etching of the gate layer forms a second side of the gate facing the drain of the lateral MOS device, and also etches a cavity extending partway underneath the second side of the gate. A dielectric layer is formed at least on the first and second sides of the gate and filling the cavity extending partway underneath the second side of the gate.

Abstract: Disclosed is processes for producing amide compounds, and their crystalline and salts form. Herein, one of the amide compounds is represented by the following formula (1): which is characterized by an X-ray diffraction (XRD) pattern having peaks at about 14.2, 15.6, 16.4, 20.1, 20.5 and 21.2°±0.2° 2?.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of gate stack structures, and an ILD. The substrate includes an active region. The gate stack structures are disposed on the active region of the substrate. The isolation structure is embedded within the substrate and surrounding the active region. The ILD covers the gate stack structures. The ILD includes a first protruding portion protruding toward the isolation structure.

Abstract: A method for preparing a carbon nanodot-fluorescent polymer composite includes subjecting a reactant and a biological component to a reaction at 260° C. to 290° C., so as to obtain the carbon nanodot-fluorescent polymer composite containing a polymer and carbon nanodots dispersed in the polymer. The biological component includes at least one of collagen, chitin, gelatin, and sodium alginate. The reactant is selected from a reaction component or a polycondensate formed therefrom. The reaction component includes terephthalic acid and ethylene glycol capable of reacting with carboxylic acid groups of the terephthalic acid. Also disclosed are the carbon nanodot-fluorescent polymer composite and a carbon nanodot-fluorescent composite fiber including the same.

Abstract: A method for generating multimedia content is provided. The method includes receiving voice data that includes a recording of a voice of a user, receiving a selection of one character from among a plurality of characters from the user, and transmitting a multimedia content generated based on the voice data, a state of the user identified based on the voice data, and the selected character to another user.

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

Abstract: A lighting keyboard is provided with at least one keyswitch, a support plate and a backlight module. The keyswitch has a keycap and a switch under the keycap. The support plate connects beneath the keycap by a support mechanism. The backlight module has a lighting board configured underneath the support plate and corresponding to the keycap. The lighting board includes a board, a first reflective layer and a circuit layer. The circuit layer is disposed on the board and includes a concave-convex structure and circuit traces. The circuit traces electrically connects with a light emitting unit. The first reflective layer covers the concave-convex structure to form microstructure regions.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate. A gate structure overlies a substrate between a source region and a drain region. A drift region is disposed laterally between the gate structure and the drain region. A first dielectric layer overlies the substrate. A field plate is disposed within the first dielectric layer between the gate structure and the drain region. A conductive wire overlies the first dielectric layer and contacts the field plate. At least a portion of the conductive wire directly overlies a first sidewall of the drift region.

Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.

Abstract: A method includes receiving a carrier, the carrier including a carrier body, a first filter, and a housing securing the first filter to the carrier body. The method further includes uninstalling the housing from the carrier, replacing the first filter with a second filter, reinstalling the housing on the carrier body, and inspecting the second filter. Inspecting the second filter includes using an automatic inspection mechanism to detect surface flatness of the second filter.

Abstract: Disclosed is a fluid control device for de-vacuuming in a wafer grinding apparatus. The fluid control device has a linear driver which drives a positioning seat to move upward and downward, several drain tubes are respectively disposed in the positioning seat, several flexible covers are respectively attached to each of the drain tubes, a converting seat is disposed on a support frame, and several flow diverters are arranged at intervals on the support frame. Several relay channels are formed within the converting seat and each of the flexible covers corresponds with each of the relay channels individually, the other end of each relay channel communicates with several relay tubes. Each flow diverter is connected to several conveying tubes, and communicates with several conveying tubes correspondingly, whereby the flow is controlled to enter the wafer grinding apparatus between the upper grinding wheel and the wafer subjected to the grinding thereof.

Abstract: A multi-mold block drive device includes a guide seat having a plurality of spaced-apart guide holes extending through inner and outer peripheral surfaces thereof, a plurality of speed reduction drive units each including a speed reducer driven by a servo motor and having an eccentric shaft, and a plurality of mold locking units each connected between one of the guide holes and a corresponding speed reduction drive unit. Each mold locking unit includes a pivot shaft, a linkage disposed between the pivot shaft and the corresponding guide hole, and a guide rod pivoted to the linkage. The linkage includes a crank driven by the eccentric shaft, a first link arm pivoted between the crank and the pivot shaft, and a second link arm pivoted between the crank and the guide rod. An injection molding machine having the multi-mold block drive device is also disclosed.

Abstract: An illuminating circuit structure includes a film sheet, an illuminant, a printed baseline layer, and a printed pad layer. The printed baseline layer includes a first baseline segment and a second baseline segment printed on the film sheet, while the printed pad layer includes a first bar pad and a second bar pad. For a first baseline head of the first baseline layer and a first pad head of the first bar pad, one of which extends along a first direction and the other of which extends along a second direction not parallel to the first direction. Therefore, the first baseline segment and the first bar pad achieve electrical connection despite of an existed print shifting. Similarly, a second baseline head of the second baseline layer and a second pad head of the second bar pad also can achieve electrical connection despite of an existed print shifting.

Abstract: In a method of fabricating an electronic device, a first nMOS device structure and a second nMOS device structure are formed. Each nMOS device structure includes a gate oxide disposed on a p-type base material and a gate disposed on the gate oxide. N-type dopant implantation is performed to form source and drain regions in the p-type substate of the first nMOS device structure and source and drain regions in the p-type substate of the second nMOS device structure, and to further dope the gate of the first nMOS device structure n-type to form a first nMOS device with the gate doped n-type. P-type dopant implantation is performed to dope the gate of the second nMOS device structure p-type to form the second nMOS device structure with the gate anti-doped p-type.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a gate electrode disposed on a substrate between a pair of source/drain regions. A dielectric layer is over the substrate. A field plate is disposed on the dielectric layer and laterally between the gate electrode and a first source/drain region in the pair of source/drain regions. The field plate comprises a first field plate layer and a second field plate layer. The second field plate layer extends along sidewalls and a bottom surface of the first field plate layer. The first and second field plate layers comprise a conductive material.

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

Abstract: An illuminated touchpad includes a panel, a light guide layer and a circuit board. The panel includes a first light transmitting region and a second light transmitting region. The light guide layer includes a first light guide region and a second light guide region. The circuit board includes a controller, a touch module, a first light source and a second light source. The controller controls the first light source to emit light, such that the first light guide region guides the light emitted by the first light source to the first light transmitting region. When the touch module senses that the first light transmitting region is touched, the controller controls the second light source to emit light, such that the second light guide region guides the light emitted by the second light source to the second light transmitting region.

Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

Abstract: A method includes: generating a designed mask overlay mark associated with an actual mask overlay mark to be formed in a mask; forming the actual mask overlay mark in the mask based on the designed mask overlay mark, the actual mask overlay mark including a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask overlay mark; forming an alignment of the mask by a mask metrology apparatus including a light source having a wavelength and a numerical aperture, wherein a pitch between adjacent two of the plurality of overlay patterns does not exceed the wavelength divided by twice the numerical aperture; and forming a pattern in a layer of a wafer by transferring the device feature pattern while the mask is under the alignment.