Abstract: An integrated circuit includes a first circuit, formed based on one or more Group III-V compound materials, that is configured to operate with a first voltage range. The integrated circuit includes a second circuit, also formed based on the one or more Group III-V compound materials, that is operatively coupled to the first circuit and configured to operate with a second voltage range, wherein the second voltage range is substantially higher than the first voltage range. The integrated circuit includes a set of first test terminals connected to the first circuit. The integrated circuit includes a set of second test terminals connected to the second circuit. Test signals applied to the set of first test terminals and to the set of second test terminals, respectively, are independent from each other.

Abstract: Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.

Abstract: This disclosure is directed to a circuit that includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and configured to trigger in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a remaining current passing through the rectifier circuit.

Abstract: An integrated circuit includes a first circuit, formed based on one or more Group III-V compound materials, that is configured to operate with a first voltage range. The integrated circuit includes a second circuit, also formed based on the one or more Group III-V compound materials, that is operatively coupled to the first circuit and configured to operate with a second voltage range, wherein the second voltage range is substantially higher than the first voltage range. The integrated circuit includes a set of first test terminals connected to the first circuit. The integrated circuit includes a set of second test terminals connected to the second circuit. Test signals applied to the set of first test terminals and to the set of second test terminals, respectively, are independent from each other.

Abstract: An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.

Abstract: The present disclosure describes a semiconductor device having artificial field plates. The semiconductor device includes a first gallium nitride (GaN) layer on a substrate, an aluminum gallium nitride (AlGaN) layer on the first GaN layer, and a second GaN layer on the AlGaN layer. The first and second GaN layers includes different types of dopants. The semiconductor device further includes a gate contact structure in contact with the second GaN layer, first and second source/drain (S/D) contact structures in contact with the AlGaN layer, one or more artificial field plates between the gate contact structure and the first S/D contact structure. The first and second S/D contact structures are disposed at opposite sides of the gate contact structure. The one or more artificial field plates are separated from the first and second S/D contact structures and above the AlGaN layer.

Abstract: A semiconductor device includes in a transistor layer, components of corresponding transistors (transistor components); in corresponding layers below the transistor layer (sub-TR layers), various non-dummy structures (non-dummy sub-TR structures) coupled to the transistor components and which are included because the semiconductor device has a buried power rail (BPR) architecture; and in corresponding layers over the transistor layer (supra-TR layers), various dummy structures (dummy supra-TR structures) which are included as artifacts resulting from the semiconductor device being based on a dual-architecture-compatible design which is substantially equally suitable either to adaptation into a non-BPR architecture or adaptation into the BPR architecture; and the semiconductor device being an inductor.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, and a circuit over the first side of the substrate and including a first transistor and a second transistor. A first terminal of the first transistor is electrically coupled to a second terminal of the second transistor both over the first side of the substrate and under the second side of the substrate.

Abstract: Methods and semiconductor devices are described herein which eliminate the use of additional masks. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer.

Abstract: Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

Abstract: Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device comprising a plurality of quasi field plates (QFPs) for enhanced wafer uniformity and performance. A channel layer and a barrier layer are stacked on a substrate, and the channel layer accommodates a two-dimensional carrier gas (2DCG). A source electrode, a drain electrode, and a gate electrode overlie the channel and barrier layers, and the gate electrode is between the source and drain electrodes in a first direction. The plurality of QFPs are between the gate electrode and the drain electrode. Further, the plurality of QFPs are capacitively or directly electrically coupled to the drain electrode, and are spaced from each other laterally in a line in a second direction transverse to the first direction.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first transistor and a second transistor over the first side of the substrate, a first conductive pattern over the first side of the substrate, and a second conductive pattern under the second side of the substrate. The first conductive pattern electrically couples a first terminal of the first transistor to a second terminal of the second transistor. The second conductive pattern electrically couples the first terminal of the first transistor to the second terminal of the second transistor.

Abstract: Methods and semiconductor devices are described herein which eliminate the use of additional masks. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer.

Abstract: Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

Abstract: A switching circuit includes a main circuit including a number of first transistors. The main circuit has a first node, a second node, and a third node and is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. The switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit. The auxiliary circuit includes a second transistor. A breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the number of first transistors.

Abstract: A semiconductor package includes a plurality of semiconductor chips. The semiconductor package includes a redistribution structure. The redistribution structure can be configured to electrically couple the plurality of semiconductor chips to each other, and further configured to transmit a single global clock signal. Data transferred across the plurality of semiconductor chips can be synchronized in a clock domain to which the single global clock signal belongs.