Patents by Inventor Cheng-Hsiang Hsieh

Cheng-Hsiang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200333320
    Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.
    Type: Application
    Filed: June 11, 2020
    Publication date: October 22, 2020
    Inventors: Kun-Lung Chen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Jui-Cheng Huang
  • Patent number: 10784872
    Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 10749537
    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Chih-Hsien Chang, Ruey-Bin Sheen, Cheng-Hsiang Hsieh
  • Publication number: 20200252247
    Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.
    Type: Application
    Filed: January 13, 2020
    Publication date: August 6, 2020
    Inventors: Chaitanya Palusa, Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh
  • Publication number: 20200252248
    Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.
    Type: Application
    Filed: January 13, 2020
    Publication date: August 6, 2020
    Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
  • Patent number: 10712333
    Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kun-Lung Chen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Jui-Cheng Huang
  • Publication number: 20200153478
    Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Inventors: Po-Hsiang LAN, Cheng-Hsiang HSIEH
  • Publication number: 20200127668
    Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Ting-Kuei KUAN, Cheng-Hsiang HSIEH, Chen-Ting KO, Ruey-Bin SHEEN, Chih-Hsien CHANG
  • Publication number: 20200127648
    Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Tsung-Hsien TSAI, Ruey-Bin SHEEN, Chih-Hsien CHANG, Cheng-Hsiang HSIEH
  • Publication number: 20200091919
    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.
    Type: Application
    Filed: November 20, 2019
    Publication date: March 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien TSAI, Chih-Hsien CHANG, Ruey-Bin SHEEN, Cheng-Hsiang HSIEH
  • Patent number: 10541718
    Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsiang Lan, Cheng-Hsiang Hsieh
  • Publication number: 20200004137
    Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 2, 2020
    Inventors: Ru-Gun LIU, Chin-Hsiang LIN, Cheng-I HUANG, Chih-Ming LAI, Lai Chien WEN, Ken-Hsien HSIEH, Shih-Ming CHANG, Yuan-Te HOU
  • Patent number: 10523218
    Abstract: Track-and-hold charge pumps and PLL are provided. A track-and-hold charge pump includes a track-and-hold circuit, a transconductance amplifier, a pulse width modulator (PWM), and a pumping switch coupled to the transconductance amplifier. The track-and-hold circuit samples an input signal according to a reference clock. The transconductance amplifier converts the sampled input signal into a current. The PWM provides a PWM signal according to the reference clock. The pumping switch is controlled by the PWM signal, to provide an output current according to the current.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Kuei Kuan, Cheng-Hsiang Hsieh, Chen-Ting Ko, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 10523221
    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Chih-Hsien Chang, Ruey-Bin Sheen, Cheng-Hsiang Hsieh
  • Patent number: 10516385
    Abstract: A ring oscillator is provided. The ring oscillator includes a pseudo pass-gate inverter, a third transistor, a fourth transistor and a delay chain. The pseudo pass-gate inverter includes a first transistor and a second transistor in series. The third transistor is connected in series with the pseudo pass-gate inverter. The drain of the fourth transistor is connected to an output of the pseudo pass-gate inverter. The gate of the fourth transistor is connected to the gate of the third transistor to receive the realignment signal. The delay chain includes a plurality of delay cells. An input of the delay chain is connected to the output of the pseudo pass-gate inverter. When the realignment signal is in a realignment state, the third transistor is turned off, the fourth transistor is turned on.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 10476192
    Abstract: An electrical connector includes an insulator body including a mating cavity formed by a top plate, a bottom plate and two lateral plates. Two surfaces of the top plate and the bottom plate facing each other have a plurality of terminal trenches. A plurality of conductive terminals are respectively arranged in the terminal trenches of the insulator body. Each of the conductive terminals has a contact portion, a welding portion and a main body portion connected to the contact portion and the welding portion. The welding portions extend out of the insulator body respectively. Each of thicknesses of the contact portions is less than each of thicknesses of the main body portions, or each of widths of the contact portions is less than each of widths of the main body portions.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: November 12, 2019
    Assignee: SPEED TECH CORP.
    Inventors: Kuo-Hua Huang, Cheng-Hsiang Hsueh, I-Ting Hsieh
  • Publication number: 20190221639
    Abstract: A method for fabrication a nanosheet device includes providing forming a stacked layer on a substrate, having first material layers and second material layers in different materials, alternatingly stacked up. The stacked layer is patterned to a stacked fin. A dummy stack is formed on the stacked fin. An etching back process is performed with the dummy stack with spacers to etch the stacked fin and expose the substrate. Laterally etches the first material layers and the second material layers, to have indent portions. Inner spacers fill the indent portions. A first/second source/drain layer is formed on the substrate at both sides of the dummy stack. Etching process is performed to remove the dummy gate of the dummy stack and the selected one of the first material layers and the second material layers between the inner spacers. Metal layer fills between the spacers and the inner spacers.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Kuan-Hao Tseng, Yu-Hsiang Lin, Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Chueh-Fei Tai, Cheng-Ping Kuo
  • Publication number: 20190173516
    Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.
    Type: Application
    Filed: January 29, 2019
    Publication date: June 6, 2019
    Inventors: Po-Hsiang LAN, Cheng-Hsiang Hsieh
  • Publication number: 20190158102
    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien TSAI, Chih-Hsien CHANG, Ruey-Bin SHEEN, Cheng-Hsiang HSIEH
  • Patent number: D873834
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 28, 2020
    Assignee: ACER INCORPORATED
    Inventors: Ju-Hsien Weng, Tzu-Hsiang Chang, Te-Ho Chen, Hsing-Yi Kao, Chien-Yu Hsieh, Wei-Yi Li, Yi-Ming Chang, Lun-Yu Hung, Cheng-Yu Cheng