Abstract: Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Abstract: A fluidic cartridge and methods of operation are described. The fluidic cartridge includes a substrate having a plurality of contact pads designed to electrically couple with an analyzer, a semiconductor chip having a sensor array, and a reference electrode. The fluidic cartridge includes a first fluidic channel having an inlet and coupled to a second fluidic channel, the second fluidic channel being aligned such that the sensor array and the reference electrode are disposed within the second fluidic channel. A first plug is disposed at the first inlet. The first plug includes a compliant material configured to be punctured by a capillary without leaking fluid through the first plug.

Abstract: Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

Abstract: A biologically sensitive field effect transistor includes a substrate, a first control gate and a second control gate. The substrate has a first side and a second side opposite to the first side, a source region and a drain region. The first control gate is disposed on the first side of the substrate. The second control gate is disposed on the second side of the substrate. The second control gate includes a sensing film disposed on the second side of the substrate. A voltage biasing between the source region and the second control gate is smaller than a threshold voltage of the second control gate.

Abstract: Biosensor devices and methods of forming the same are provided. A cavity is formed in a substrate and is configured to receive one or more charged molecules. A transistor is formed in the substrate and includes a source region, a drain region, and a channel region that are spatially separated from the cavity in a lateral direction. A gate of the transistor is disposed below the cavity and extends between the cavity and the source, drain, and channel regions. A voltage potential of the gate is based on a number of the charged molecules in the cavity.

Abstract: An on-chip heater in a concentric rings configuration having non-uniform spacing between heating elements provides improved radial temperature uniformity and low power consumption compared to circular or square heating elements. On-chip heaters are suitable for integration and use with on-chip sensors that require tight temperature control.

Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider and a track-and-hold charge pump. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to provide a feedback signal according to the output clock. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The track-and-hold charge pump includes a track-and-hold circuit, a pumping switch and a pulse width modulator (PWM). The track-and-hold circuit is coupled to the frequency divider and configured to sample the feedback signal according to the reference clock. The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the sampled feedback signal.

Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to an input of a delay chain of the ring oscillator. The second and third transistors are coupled in series and gates of the second and third transistors are configured to receive an output signal of the delay chain. When the first transistor is turned off and the fourth transistor is turned on, the node is pulled to a first logic level from a second logic level in order to align a phase of a waveform of the ring oscillator.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: A biologically sensitive field effect transistor includes a substrate, a first control gate and a second control gate. The substrate has a first side and a second side opposite to the first side, a source region and a drain region. The first control gate is disposed on the first side of the substrate. The second control gate is disposed on the second side of the substrate. The second control gate includes a sensing film disposed on the second side of the substrate. A voltage biasing between the source region and the second control gate is smaller than a threshold voltage of the second control gate.

Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-signal modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

Abstract: Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.

Abstract: An on-chip heater in a concentric rings configuration having non-uniform spacing between heating elements provides improved radial temperature uniformity and low power consumption compared to circular or square heating elements. On-chip heaters are suitable for integration and use with on-chip sensors that require tight temperature control.

Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.

Abstract: Methods and semiconductor devices are described herein which eliminate the use of additional masks. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer.