Abstract: An embodiment of a method for control of signal level is disclosed. In such an embodiment, a number for a pre-cursor set, a number for a cursor set, and a number for a post-cursor set are set corresponding to a weighted contribution of a pre-cursor symbol, a weighted contribution of a cursor symbol, and a weighted contribution of a post-cursor symbol, respectively, for the signal level. A number associated with a high-impedance set is determined. The number associated with the high-impedance set is determined by subtracting the number for the pre-cursor set, the number for the cursor set, and the number for the post-cursor set from a total available amount of units. The high-impedance set provides no weighted contribution to the signal level. Data is transmitted using the signal level set responsive to the pre-cursor set, the cursor set, and the post-cursor set.

Abstract: In one embodiment, a receiver circuit is provided. The receiver circuit includes a low-power equalization circuit having a first linear equalization circuit coupled to receive serial data. The receiver circuit includes a low-noise equalization circuit having a second linear equalization circuit coupled to receive the serial data, and a non-linear equalization circuit coupled to an output of the second linear equalization circuit. The receiver circuit includes a control circuit configured to enable the low-power equalization circuit and disable the low-noise equalization circuit in response to a first state of a control signal. The control circuit is configured to disable the low-power equalization circuit and enable the low-noise equalization circuit in response to a second state of the control signal.

Abstract: A clock data recovery module and a method of operation thereof are described. In an embodiment, a data stream is received. Transitions in the data stream are detected to provide phase signaling for indicating phase relationships to the transitions detected. A lock detector receives the phase signaling. The lock detector accumulates phase information from the phase signaling and temporarily stores an accumulated total of the phase information representative of a code change, and the lock detector determines whether the code change is within a set range over a time period and resets the accumulated total at a conclusion of the time period.

Abstract: A phase interpolator is described. The phase interpolator can have a code-to-bias converter, and a phase interpolation interface. In an embodiment of a code-to-bias converter, a single digital-to-analog converter is provided to generate bias signaling associated with phase signals. A bleeder current source is provided to generate a bleeder current, where the bleeder current is selected responsive to phase so the phase signals do not reach zero current.

Abstract: In one embodiment of the invention, a circuit arrangement is provided. The circuit arrangement includes a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second differential amplifier. Each differential amplifier includes an adjustable current control circuit coupled to limit a tail current passing through the differential amplifier.

Abstract: A signal-aligning circuit includes a phase-adjusting circuit, a first control circuit, a second control circuit, and a tuning circuit. The first control circuit outputs a first voltage signal reflecting a phase difference between a first input signal (reference signal) and a second input signal (adjusted signal) and having a static phase offset due to asymmetries in the first control circuit. The second control circuit is a replica of the first control circuit, and receives the reference signal at two inputs thereof and outputs a second voltage signal reflecting the same static phase offset. The tuning circuit compares the first and second voltage signals and tunes a bias current in the first and second control circuits, whereby the static phase offsets of the first and the second control circuits becomes zero when the adjusted signal is phase-aligned with the reference signal in the steady state.