Patents by Inventor Cheng-Hsien Cheng

Cheng-Hsien Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210104439
    Abstract: A memory device includes a substrate, a stacked structure, a plurality of channel structures, a plurality of memory layers, and a plurality of shallow isolation structures. The substrate has an upper surface. The stacked structure is disposed on an upper surface of the substrate, wherein the stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternatively stacked on the upper surface. The channel structures penetrate portions of the stacked structure and are electrically connected to the substrate. The memory layers surround the corresponding ones of the channel structures. The shallow isolation structures extend from a top surface of the stacked structure toward the substrate, wherein each of the shallow isolation structures includes a substance having a dielectric constant of less than 3.9.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 8, 2021
    Inventors: Shaw-Hung KU, Cheng-Hsien CHENG, Wen-Jer TSAI
  • Patent number: 10796753
    Abstract: A method for determining quick-pass-write (QPW) operation in increment-step-program-pulse (ISPP) operation is provided. The QPW operation is simultaneously applying a bit line voltage during the ISPP operation. The method includes, according to bit line voltages varying in a first range and voltage difference values varying in a second range with respect to a verified voltage, estimating a shrinkage quantity of threshold voltage distribution width at each bit line voltage and each voltage difference value, so as to obtain a shrinkage-quantity topographic contour. According to the bit line voltages and the voltage difference values, a program shot number as needed to achieve the verified voltage is estimated, so as to obtain a program-shot-number topographic contour.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: October 6, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hung Huang, Cheng-Hsien Cheng, Shaw-Hung Ku, Yin-Jen Chen
  • Patent number: 10644018
    Abstract: A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 5, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Atsuhiro Suzuki
  • Patent number: 10460797
    Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: October 29, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shaw-Hung Ku, Ta-Wei Lin, Cheng-Hsien Cheng, Chih-Wei Lee, Wen-Jer Tsai
  • Publication number: 20190319033
    Abstract: A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 17, 2019
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei LEE, Cheng-Hsien CHENG, Shaw-Hung KU, Atsuhiro SUZUKI
  • Publication number: 20190304556
    Abstract: The method for programming a non-volatile memory includes the following steps. Perform a program and program verify operation for a memory cell in the non-volatile memory, wherein the program and program verify operation includes applying a sequence of incremental step pulses to the memory cell. Perform a post-verifying operation for the memory cell after the memory cell passes the program and program verify operation. Apply a post-programming pulse to the memory cell if the memory cell fails the post-verifying operation, wherein the amplitude of the post-programming pulse is greater than the amplitude of the last pulse in the sequence of incremental step pulses. Perform a read operation to the non-volatile memory to obtain a failed bit count corresponding to the read operation. Adjust a read reference voltage of the read operation to minimize the failed bit count.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Shaw-Hung KU, Ta-Wei LIN, Cheng-Hsien CHENG, Chih-Wei LEE, Wen-Jer TSAI
  • Patent number: 10340017
    Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 2, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shaw-Hung Ku, Yu-Hung Huang, Cheng-Hsien Cheng, Chih-Wei Lee, Atsuhiro Suzuki, Wen-Jer Tsai
  • Publication number: 20190139615
    Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.
    Type: Application
    Filed: November 6, 2017
    Publication date: May 9, 2019
    Inventors: Shaw-Hung KU, Yu-Hung HUANG, Cheng-Hsien CHENG, Chih-Wei LEE, Atsuhiro SUZUKI, Wen-Jer TSAI
  • Publication number: 20190080750
    Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Inventors: Shaw-Hung Ku, Ta-Wei Lin, Cheng-Hsien Cheng, Chih-Wei Lee, Wen-Jer Tsai
  • Patent number: 9786794
    Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: October 10, 2017
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
  • Publication number: 20170098478
    Abstract: A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Wen-Pin Lu
  • Publication number: 20170077118
    Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 16, 2017
    Inventors: CHENG-HSIEN CHENG, CHIH-WEI LEE, SHAW-HUNG KU, WEN-PIN LU
  • Patent number: 9589982
    Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: March 7, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
  • Patent number: 9548121
    Abstract: Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n?1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 17, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Wei Lee, Shaw-Hung Ku, Cheng-Hsien Cheng
  • Publication number: 20160372198
    Abstract: Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n?1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.
    Type: Application
    Filed: June 18, 2015
    Publication date: December 22, 2016
    Inventors: Chih-Wei LEE, Shaw-Hung KU, Cheng-Hsien CHENG
  • Patent number: 9524784
    Abstract: The present invention provides methods and associated devices for controlling the voltage threshold distribution corresponding to performing a function on cells of non-volatile memory device. In one embodiment, a method is provided. The method may comprise providing the non-volatile memory device. The device comprises one or more strings, each string comprising a plurality of cells, the plurality of cells comprising a first cell and a second cell. The method further comprises performing a function of the non-volatile memory device by applying a first function voltage to the first cell and a second function voltage to the second cell. The first function voltage and the second function voltage are different.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: December 20, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
  • Publication number: 20160336339
    Abstract: Embodiments of the present invention provide improved 3D non-volatile memory devices and associated methods. In one embodiment, a string of 3D non-volatile memory cells is provided. The string comprises a core extending along an axis of the string, the core having an elliptical cross section in a plane perpendicular to the axis; and a plurality of word lines, each word line disposed around a part of the core, the plurality of word lines spaced along the axis, and each word line corresponding to one of the memory cells. In various embodiments, at least one operating parameter is defined in order to improve the operation of the 3D non-volatile memory device.
    Type: Application
    Filed: October 13, 2015
    Publication date: November 17, 2016
    Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
  • Patent number: 9437612
    Abstract: A three-dimensional memory, which includes memory cell stacked structures. The memory cell stacked structures are stacked by a plurality of memory cell array structures and insulation layers alternatively, and each memory cell array structure includes word lines, active layers, composite layers and sources/drains. The word lines, the active layers and the composite layers extend along a Y direction. The active layers are disposed between the adjacent word lines. The composite layers are disposed between the adjacent word lines and the adjacent active layers, and each composite layer includes a first dielectric layer, a charge storage layer and a second dielectric layer in sequence from the active layers. The sources/drains are disposed in the active layers at equal intervals. A memory cell includes two adjacent sources/drains, the active layer between the two adjacent sources/drains, the first dielectric layer, the charge storage layer and the second dielectric layer on the active layer, and the word lines.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 6, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Wen-Pin Lu
  • Publication number: 20160225911
    Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.
    Type: Application
    Filed: April 11, 2016
    Publication date: August 4, 2016
    Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
  • Patent number: D873834
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 28, 2020
    Assignee: ACER INCORPORATED
    Inventors: Ju-Hsien Weng, Tzu-Hsiang Chang, Te-Ho Chen, Hsing-Yi Kao, Chien-Yu Hsieh, Wei-Yi Li, Yi-Ming Chang, Lun-Yu Hung, Cheng-Yu Cheng