Patents by Inventor Cheng-Hsien Cheng
Cheng-Hsien Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9524784Abstract: The present invention provides methods and associated devices for controlling the voltage threshold distribution corresponding to performing a function on cells of non-volatile memory device. In one embodiment, a method is provided. The method may comprise providing the non-volatile memory device. The device comprises one or more strings, each string comprising a plurality of cells, the plurality of cells comprising a first cell and a second cell. The method further comprises performing a function of the non-volatile memory device by applying a first function voltage to the first cell and a second function voltage to the second cell. The first function voltage and the second function voltage are different.Type: GrantFiled: September 9, 2015Date of Patent: December 20, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
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Publication number: 20160336339Abstract: Embodiments of the present invention provide improved 3D non-volatile memory devices and associated methods. In one embodiment, a string of 3D non-volatile memory cells is provided. The string comprises a core extending along an axis of the string, the core having an elliptical cross section in a plane perpendicular to the axis; and a plurality of word lines, each word line disposed around a part of the core, the plurality of word lines spaced along the axis, and each word line corresponding to one of the memory cells. In various embodiments, at least one operating parameter is defined in order to improve the operation of the 3D non-volatile memory device.Type: ApplicationFiled: October 13, 2015Publication date: November 17, 2016Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
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Patent number: 9437612Abstract: A three-dimensional memory, which includes memory cell stacked structures. The memory cell stacked structures are stacked by a plurality of memory cell array structures and insulation layers alternatively, and each memory cell array structure includes word lines, active layers, composite layers and sources/drains. The word lines, the active layers and the composite layers extend along a Y direction. The active layers are disposed between the adjacent word lines. The composite layers are disposed between the adjacent word lines and the adjacent active layers, and each composite layer includes a first dielectric layer, a charge storage layer and a second dielectric layer in sequence from the active layers. The sources/drains are disposed in the active layers at equal intervals. A memory cell includes two adjacent sources/drains, the active layer between the two adjacent sources/drains, the first dielectric layer, the charge storage layer and the second dielectric layer on the active layer, and the word lines.Type: GrantFiled: August 21, 2015Date of Patent: September 6, 2016Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Wen-Pin Lu
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Publication number: 20160225911Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.Type: ApplicationFiled: April 11, 2016Publication date: August 4, 2016Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
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Patent number: 9349878Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.Type: GrantFiled: June 24, 2014Date of Patent: May 24, 2016Assignee: MACRONIX International Co., Ltd.Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
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Patent number: 9324431Abstract: A nonvolatile memory cell has a semiconductor substrate, a multilayer stack including a charge trapping layer over a floating gate, a top conductive layer, and circuitry controlling program and erase operations on the nonvolatile memory cell. The program and erase operations change a first charge density on the floating gate by a larger magnitude than a second charge density on the charge trapping dielectric layer.Type: GrantFiled: January 27, 2015Date of Patent: April 26, 2016Assignee: Macronix International Co., Ltd.Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai
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Patent number: 9209316Abstract: A read only memory including a substrate, a source region and a drain region, a charge storage structure, a gate, and a local extreme doping region is provided. The source region and the drain region are disposed in the substrate, the charge storage structure is located on the substrate between the source region and the drain region, and the gate is configured on the charge storage structure. The local extreme doping region is located in the substrate between the source region and the drain region and includes a low doping concentration region and at least one high doping concentration region. The high doping concentration region is disposed between the low doping concentration region and one of the source region and the drain region, and a doping concentration of the high doping concentration region is three times or more than three times a doping concentration of the low doping concentration region.Type: GrantFiled: March 15, 2012Date of Patent: December 8, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Chieh Cheng, Cheng-Hsien Cheng, Wen-Jer Tsai
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Patent number: 9048263Abstract: A non-volatile memory and a manufacturing method thereof are provided. In this method, a first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the pair of charge storage spacers. A conductive layer is formed on the second oxide layer, wherein the conductive layer is located completely on the top of the pair of charge storage spacers.Type: GrantFiled: June 25, 2014Date of Patent: June 2, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Cheng-Hsien Cheng, Wen-Jer Tsai
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Patent number: 9018085Abstract: A method for fabricating a memory device of this invention includes at least the following steps. A tunnel dielectric layer is formed over a substrate. A gate is fowled over the tunnel dielectric layer. At least one charge storage layer is formed between the gate and the tunnel dielectric layer. Two doped regions are formed in the substrate beside the gate. A word line is formed on and electrically connected to the gate, wherein the word line having a thickness greater than a thickness of the gate.Type: GrantFiled: March 5, 2014Date of Patent: April 28, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Shih-Guei Yan, Wen-Jer Tsai, Cheng-Hsien Cheng
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Publication number: 20140306282Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.Type: ApplicationFiled: June 24, 2014Publication date: October 16, 2014Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
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Publication number: 20140308791Abstract: A non-volatile memory and a manufacturing method thereof are provided. In this method, a first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the pair of charge storage spacers. A conductive layer is formed on the second oxide layer, wherein the conductive layer is located completely on the top of the pair of charge storage spacers.Type: ApplicationFiled: June 25, 2014Publication date: October 16, 2014Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Cheng-Hsien Cheng, Wen-Jer Tsai
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Patent number: 8796754Abstract: A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.Type: GrantFiled: June 22, 2011Date of Patent: August 5, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
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Patent number: 8791522Abstract: A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer.Type: GrantFiled: October 12, 2011Date of Patent: July 29, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Cheng-Hsien Cheng, Wen-Jer Tsai
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Publication number: 20140187032Abstract: A method for fabricating a memory device of this invention includes at least the following steps. A tunnel dielectric layer is formed over a substrate. A gate is fowled over the tunnel dielectric layer. At least one charge storage layer is formed between the gate and the tunnel dielectric layer. Two doped regions are formed in the substrate beside the gate. A word line is formed on and electrically connected to the gate, wherein the word line having a thickness greater than a thickness of the gate.Type: ApplicationFiled: March 5, 2014Publication date: July 3, 2014Applicant: MACRONIX International Co., Ltd.Inventors: Shih-Guei Yan, Wen-Jer Tsai, Cheng-Hsien Cheng
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Patent number: 8698222Abstract: A memory device is described, including a tunnel dielectric layer over a substrate, a gate over the tunnel dielectric layer, at least one charge storage layer between the gate and the tunnel dielectric layer, two doped regions in the substrate beside the gate, and a word line that is disposed on and electrically connected to the gate and has a thickness greater than that of the gate.Type: GrantFiled: November 24, 2011Date of Patent: April 15, 2014Assignee: Macronix International Co., Ltd.Inventors: Shih-Guei Yan, Wen-Jer Tsai, Cheng-Hsien Cheng
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Publication number: 20130240975Abstract: A read only memory including a substrate, a source region and a drain region, a charge storage structure, a gate, and a local extreme doping region is provided. The source region and the drain region are disposed in the substrate, the charge storage structure is located on the substrate between the source region and the drain region, and the gate is configured on the charge storage structure. The local extreme doping region is located in the substrate between the source region and the drain region and includes a low doping concentration region and at least one high doping concentration region. The high doping concentration region is disposed between the low doping concentration region and one of the source region and the drain region, and a doping concentration of the high doping concentration region is three times or more than three times a doping concentration of the low doping concentration region.Type: ApplicationFiled: March 15, 2012Publication date: September 19, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Chieh Cheng, Cheng-Hsien Cheng, Wen-Jer Tsai
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Publication number: 20130134498Abstract: A memory device is described, including a tunnel dielectric layer over a substrate, a gate over the tunnel dielectric layer, at least one charge storage layer between the gate and the tunnel dielectric layer, two doped regions in the substrate beside the gate, and a word line that is disposed on and electrically connected to the gate and has a thickness greater than that of the gate.Type: ApplicationFiled: November 24, 2011Publication date: May 30, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shih-Guei Yan, Wen-Jer Tsai, Cheng-Hsien Cheng
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Publication number: 20130092997Abstract: A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer.Type: ApplicationFiled: October 12, 2011Publication date: April 18, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Cheng-Hsien Cheng, Wen-Jer Tsai
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Publication number: 20120326222Abstract: A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.Type: ApplicationFiled: June 22, 2011Publication date: December 27, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
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Publication number: 20110079840Abstract: A memory cell is provided. The memory cell includes a substrate, an isolation layer, a gate, a charge storage structure, a first source/drain region, a second source/drain region and a channel layer. The isolation layer is disposed over the substrate. The gate is disposed over the isolation layer. The charge storage structure is disposed over the isolation layer and the gate. The first source/drain region is disposed over the charge storage structure at two sides of the gate. The second source/drain region is disposed over the charge storage structure at top of the gate. The channel layer is disposed over the charge storage structure at sidewall of the gate and is electrically connected with the first source/drain region and the second source/drain region.Type: ApplicationFiled: October 1, 2009Publication date: April 7, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jyun-Siang Huang, Wen-Jer Tsai, Tien-Fan Ou, Cheng-Hsien Cheng