Patents by Inventor Cheng-Hsien Lee

Cheng-Hsien Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11408730
    Abstract: A stress measuring device and a stress measuring method for measuring a stress distribution of an object are provided. The stress measuring method includes: receiving a first-dimension image of the object; marking an area of the first-dimension image to generate a marked area; calculating a first stress applied to the marked area and transforming the marked area to a strained marked area corresponding to a second-dimension image to generate a determination result; and calculating the stress distribution corresponding to the first-dimension image of the object according to the determination result.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: August 9, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: I-Hung Chiang, Hung-Hsien Ko, Cheng-Ta Pan, Wen-Yung Yeh, Cheng-Chung Lee
  • Patent number: 11394146
    Abstract: A connection pin for an expansion socket can be treated to improve signal (e.g., reduce noise) for high speed applications. A connection pin can be treated to have a conductive plating covering a proximal region of the connection pin. Electrical signals between an expansion card in contact with the connection pin and the circuit board to which the connection pin is coupled can pass directly through the conductive plating of the proximal region. However, the distal region of the connection pin can be treated to be devoid of the conductive plating, such as by being covered with a high dielectric loss and/or high-resistance material or through removal of the conductive plating in that region. Thus, electrical signals passing through the connection pin will tend to pass through the conductive plating rather than along the distal region of the pin. Thus, signal reflections and other artifacts and noise can be avoided.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: July 19, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventor: Cheng-Hsien Lee
  • Publication number: 20220223743
    Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first fin structure and a second fin structure over a substrate, a first source/drain feature disposed over the first fin structure and a second source/drain feature disposed over the second fin structure, a dielectric feature disposed over the first source/drain feature, and a contact structure formed over the first source/drain feature and the second source/drain feature. The contact structure is electrically coupled to the second source/drain feature and is separated from the first source/drain feature by the dielectric feature.
    Type: Application
    Filed: October 15, 2021
    Publication date: July 14, 2022
    Inventors: Chung-Hao Cai, Yen-Jun Huang, Ting Fang, Chia-Hsien Yao, Cheng-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11380986
    Abstract: A wireless communication device and method are provided. The wireless communication device includes a main body, a rotating module and an antenna module. The main body includes a housing and an RF signal module accommodated in the housing; the rotating module is accommodated in the housing and located at one side of the RF signal module, and includes a rotor motor and a rotating shaft, and the rotor motor is connected to the rotating shaft for rotating the rotating shaft; the antenna module is accommodated in the housing and disposed on the rotating shaft, and is electrically connected to the RF signal module. The wireless signal communication method includes: rotating the antenna module, determining the intensity of the RF signal received by the antenna module, and stopping the rotation of the antenna module. Therefore, the antenna module can dynamically adjust its orientation to receive the RF signal with sufficient intensity.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: July 5, 2022
    Assignee: HTC CORPORATION
    Inventors: Cheng Hung Lin, Chia Te Chien, Chun Hsien Lee
  • Patent number: 11147196
    Abstract: An air duct formed from an electromagnetic wave absorber in the form of a sheet is disclosed. The sheet can be bent into a duct or scored, and folded at the score lines to bring the ends of the sheet into proximity. The ends can then be joined by adhesive, welding, or mechanical fasters. The air ducts disclosed herein provide dual functions of providing ventilation for electronic components in an electronic module, while at the same time, reducing electromagnetic interference (EMI). One or more air ducts, of the same or different dimensions, shapes, volumes can be combined with electronic modules, such as a server, to provide both ventilation and EMI suppression to various components within the electronic module.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: October 12, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Ching-Jen Chen, Cheng-Hsien Lee
  • Publication number: 20210315136
    Abstract: An air duct formed from an electromagnetic wave absorber in the form of a sheet is disclosed. The sheet can be bent into a duct or scored, and folded at the score lines to bring the ends of the sheet into proximity. The ends can then be joined by adhesive, welding, or mechanical fasters. The air ducts disclosed herein provide dual functions of providing ventilation for electronic components in an electronic module, while at the same time, reducing electromagnetic interference (EMI). One or more air ducts, of the same or different dimensions, shapes, volumes can be combined with electronic modules, such as a server, to provide both ventilation and EMI suppression to various components within the electronic module.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 7, 2021
    Inventors: Ching-Jen CHEN, Cheng-Hsien LEE
  • Publication number: 20210313724
    Abstract: A connection pin for an expansion socket can be treated to improve signal (e.g., reduce noise) for high speed applications. A connection pin can be treated to have a conductive plating covering a proximal region of the connection pin. Electrical signals between an expansion card in contact with the connection pin and the circuit board to which the connection pin is coupled can pass directly through the conductive plating of the proximal region. However, the distal region of the connection pin can be treated to be devoid of the conductive plating, such as by being covered with a high dielectric loss and/or high-resistance material or through removal of the conductive plating in that region. Thus, electrical signals passing through the connection pin will tend to pass through the conductive plating rather than along the distal region of the pin. Thus, signal reflections and other artifacts and noise can be avoided.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 7, 2021
    Inventor: Cheng-Hsien LEE
  • Patent number: 10999929
    Abstract: The present disclosure describes expansion card interfaces for a printed circuit board and methods of making the same. The methods include forming electrical pads of the expansion card interface on a substrate, and dividing at least one electrical pad into a first portion and a second portion. The resulting expansion card interfaces have the first portion conductively coupled to a circuit on the printed circuit board, and the second portion conductively isolated from the first portion.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: May 4, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Che-Wei Chang, Cheng-Hsien Lee
  • Patent number: 10986743
    Abstract: The present disclosure describes an expansion card interface for a printed circuit board. The expansion card interface includes a substrate having an edge. The expansion card interface further includes a plurality of signal pins configured to communicate one or more signals to and from the printed circuit board. The expansion card interface further includes a plurality of ground pins adjacent to the plurality of signal pins configured to provide a ground. At least one signal pin of the plurality of signal pins extends closer to the edge of the substrate than at least one ground pin of the plurality of ground pins.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 20, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventor: Cheng-Hsien Lee
  • Publication number: 20200383205
    Abstract: The present disclosure describes expansion card interfaces for a printed circuit board and methods of making the same. The methods include forming electrical pads of the expansion card interface on a substrate, and dividing at least one electrical pad into a first portion and a second portion. The resulting expansion card interfaces have the first portion conductively coupled to a circuit on the printed circuit board, and the second portion conductively isolated from the first portion.
    Type: Application
    Filed: December 13, 2019
    Publication date: December 3, 2020
    Inventors: Che-Wei Chang, Cheng-Hsien Lee
  • Patent number: 10820410
    Abstract: A high speed circuit and a method for fabricating the same is disclosed. The high speed circuit has a printed circuit board. A pair of first and second differential traces are formed on a first surface of the printed circuit board. The differential traces carry an electrical signal. A partial loop extends through the printed circuit board. The partial loop includes first and second end slots under the first and second differential traces. The partial loop includes a pair of side slots substantially parallel to the differential traces. An anchor member connects the printed circuit board to an island formed by the first and second end slots and side slots. The anchor member forms a gap in one of the end slots or side slots. The length of the side slots and the length of the gap is selected to reduce a target common mode frequency from the electrical signal.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 27, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventor: Cheng-Hsien Lee
  • Patent number: 10784607
    Abstract: A connector assembly is disclosed to reduce discontinuity impedance between golden finger connectors and components on a circuit board. The assembly includes a circuit board including a connector edge. A plurality of connectors is formed on the connector edge on a first surface of the circuit board. A ground plane is formed on part of the circuit board on a second opposite surface of the first surface. The ground plane leaves the second opposite surface under the connector edge exposed. A ground loop is formed on the second opposite surface under at least two of the plurality of connectors.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 22, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventor: Cheng-Hsien Lee
  • Publication number: 20200288566
    Abstract: A high speed circuit and a method for fabricating the same is disclosed. The high speed circuit has a printed circuit board. A pair of first and second differential traces are formed on a first surface of the printed circuit board. The differential traces carry an electrical signal. A partial loop extends through the printed circuit board. The partial loop includes first and second end slots under the first and second differential traces. The partial loop includes a pair of side slots substantially parallel to the differential traces. An anchor member connects the printed circuit board to an island formed by the first and second end slots and side slots. The anchor member forms a gap in one of the end slots or side slots. The length of the side slots and the length of the gap is selected to reduce a target common mode frequency from the electrical signal.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Inventor: Cheng-Hsien LEE
  • Publication number: 20200275566
    Abstract: The present disclosure describes an expansion card interface for a printed circuit board. The expansion card interface includes a substrate having an edge. The expansion card interface further includes a plurality of signal pins configured to communicate one or more signals to and from the printed circuit board. The expansion card interface further includes a plurality of ground pins adjacent to the plurality of signal pins configured to provide a ground. At least one signal pin of the plurality of signal pins extends closer to the edge of the substrate than at least one ground pin of the plurality of ground pins.
    Type: Application
    Filed: December 5, 2019
    Publication date: August 27, 2020
    Inventor: Cheng-Hsien Lee
  • Publication number: 20200212610
    Abstract: A connector assembly is disclosed to reduce discontinuity impedance between golden finger connectors and components on a circuit board. The assembly includes a circuit board including a connector edge. A plurality of connectors is formed on the connector edge on a first surface of the circuit board. A ground plane is formed on part of the circuit board on a second opposite surface of the first surface. The ground plane leaves the second opposite surface under the connector edge exposed. A ground loop is formed on the second opposite surface under at least two of the plurality of connectors.
    Type: Application
    Filed: May 21, 2019
    Publication date: July 2, 2020
    Inventor: Cheng-Hsien LEE
  • Patent number: 10667384
    Abstract: A differential trace structure reducing the magnitude of low frequency attenuation is disclosed. The trace structure is formed on a printed circuit board. A pair of differential traces connects a signal receiver and a signal transmitter. A passive equalizer has a first shunt coupled to one of the pair of differential traces; and a second shunt coupled to the other one of the pair of differential traces. The passive equalizer has an inductor and a resistor coupled in series to the shunts. For low frequency signals, the passive equalizer behaves as a shunt resistance to the pair of differential traces.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 26, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventor: Cheng-Hsien Lee
  • Publication number: 20200029422
    Abstract: A differential trace structure reducing the magnitude of low frequency attenuation is disclosed. The trace structure is formed on a printed circuit board. A pair of differential traces connects a signal receiver and a signal transmitter. A passive equalizer has a first shunt coupled to one of the pair of differential traces; and a second shunt coupled to the other one of the pair of differential traces. The passive equalizer has an inductor and a resistor coupled in series to the shunts. For low frequency signals, the passive equalizer behaves as a shunt resistance to the pair of differential traces.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 23, 2020
    Inventor: Cheng-Hsien LEE
  • Publication number: 20200029434
    Abstract: This disclosure relates to a Golden Finger card design where the PCB edge has a first thickness, but the main body of the PCB is of increased thickness to accommodate application complexity. The increased thickness in the body portion provides greater dielectric material between traces, thereby reducing loss. By maintaining the edge of the PCB fingers at a first thickness, the use of existing connectors, such as standard PCIe connectors, is maintained. Golden Finger cards of this disclosure are used as a video and graphics card, network adapter card, audio adapter card, and television or other specialty adapter card.
    Type: Application
    Filed: July 23, 2018
    Publication date: January 23, 2020
    Inventors: Yu-Tsung HSU, Cheng-Hsien LEE
  • Patent number: 10499490
    Abstract: A high speed differential trace structure reducing common mode radiation is disclosed. The differential trace structure includes a first trace and a parallel second trace. A printed circuit board layer has a top surface and an opposite bottom surface. The traces are formed on the top surface. The structure includes a ground plane layer having a top layer in contact with the opposite bottom surface of the circuit board. A first void section is formed in the top layer of the ground plane layer to one side of the first trace. A second void section is formed in the top layer of the ground plane layer to one side of the second trace. The length of the second void section is determined based on a target radiation frequency. A third void section is formed in the ground plane layer that joins the first void section and the second void section.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: December 3, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventor: Cheng-Hsien Lee
  • Publication number: 20190166685
    Abstract: A high speed differential trace structure reducing common mode radiation is disclosed. The differential trace structure includes a first trace and a parallel second trace. A printed circuit board layer has a top surface and an opposite bottom surface. The traces are formed on the top surface. The structure includes a ground plane layer having a top layer in contact with the opposite bottom surface of the circuit board. A first void section is formed in the top layer of the ground plane layer to one side of the first trace. A second void section is formed in the top layer of the ground plane layer to one side of the second trace. The length of the second void section is determined based on a target radiation frequency. A third void section is formed in the ground plane layer that joins the first void section and the second void section.
    Type: Application
    Filed: February 7, 2018
    Publication date: May 30, 2019
    Inventor: Cheng-Hsien LEE