Abstract: A processing apparatus for overlay shift includes a storage unit and a control unit, and is applicable to a semiconductor wafer with several inspection regions. Each of the inspection regions has several sets of overlay marks for inspection. One set of overlay marks includes an original alignment mark without any overlay shift, and several split alignment marks with predetermined overlay shifts arranged near the original alignment mark. The original after-etch inspection (AEI) overlay data of the inspection regions is stored in the storage unit. The after-develop inspection (ADI) overlay data of the original alignment mark and the split alignment marks are compared with the original AEI overlay data by the control unit, thereby acquiring ADI pre-bias data of the original alignment mark and the split alignment marks. The control unit determines whether an overlay shift compensation is performed according to the acquired ADI pre-bias data.

Abstract: An electronic device includes an application processor and a display control circuit. The display control circuit may output a (tearing effect) TE signal to the application processor and receive an image frame from the application processor. A data processing circuit of the display control circuit generates a notification signal when the data processing circuit is ready to receive the image frame from the application processor. The timing controller generates the TE signal having a first frequency during a period from a first time point when the notification signal is received to a second time point when the application processor starts transmitting the image frame to the data processing circuit. The first frequency is greater than a reference frequency based on an output frame rate of the display control circuit.

Abstract: An electronic device includes an application processor and a display control circuit. The display control circuit may output a (tearing effect) TE signal to the application processor and receive an image frame from the application processor. A data processing circuit of the display control circuit generates a notification signal when the data processing circuit is ready to receive the image frame from the application processor. The timing controller generates the TE signal having a first frequency during a period from a first time point when the notification signal is received to a second time point when the application processor starts transmitting the image frame to the data processing circuit. The first frequency is greater than a reference frequency based on an output frame rate of the display control circuit.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: An electronic device includes a processor circuit, a frequency-domain-to-time-domain conversion circuit, a transmitter circuit, a hybrid circuit, a receiver circuit, and a time-domain-to-frequency-domain conversion circuit. The processor circuit generates a frequency-domain transmitting signal. The frequency-domain-to-time-domain conversion circuit converts the frequency-domain transmitting signal into a first time-domain transmitting signal. The transmitter circuit generates a second time-domain transmitting signal. The hybrid circuit includes an echo noise cancelling path and an echo noise path. When the echo noise cancelling path is turned off, the processor circuit receives a first frequency-domain receiving signal. When the echo noise cancelling path is turned on, the processor circuit receives a second frequency-domain receiving signal.

Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.

Abstract: The present invention discloses a signal transceiving apparatus having echo-canceling mechanism. A mixer circuit includes a Wheatstone bridge and a transformer winding circuit. The Wheatstone bridge includes another transformer winding circuit and a variable load and includes a first input terminal, a first output terminal, a second input terminal and a second output terminal located at each two neighboring arms in an order. A transmission circuit is coupled to the first input terminal and the second input terminal to perform signal transmission through the mixer circuit. A receiving circuit is coupled to the first output terminal and the second output terminal to perform signal receiving through the mixer circuit. A control circuit adjusts the impedance of the variable load when a residual echo noise amount does not satisfy a minimum echo noise amount condition, and stops to adjust the impedance when the residual echo noise amount satisfies the condition.

Abstract: An amplifier circuit includes a continuous-time linear equalizer, an adjustable gain circuit and a filter circuit. The continuous-time linear equalizer includes a first high-pass path, a first low-pass path, a second high-pass path, and a second low-pass path. The first high-pass path is used to increase a gain of a high-frequency part of a first signal source, and the second high-pass path is used to increase a gain of a high-frequency part of a second signal source. The filter circuit is used to amplify and filter the first signal source and the second signal source, and includes a fully-differential operational amplifier, a first filter network, and a second filter network.

Abstract: An echo estimation system includes a transceiver circuitry and a processor circuitry. The processor circuitry is coupled to the transceiver circuitry. The processor circuitry is configured to calculate linear echo power and non-linear echo power based on a signal under test in the transceiver circuitry. The linear echo power and the non-linear echo power are utilized to determine a quality of the transceiver circuitry or utilized to determine component parameters of the transceiver circuitry.

Abstract: The present invention discloses a signal transceiving apparatus having echo-canceling mechanism. A mixer circuit includes a Wheatstone bridge and a transformer winding circuit. The Wheatstone bridge includes another transformer winding circuit and a variable load and includes a first input terminal, a first output terminal, a second input terminal and a second output terminal located at each two neighboring arms in an order. A transmission circuit is coupled to the first input terminal and the second input terminal to perform signal transmission through the mixer circuit. A receiving circuit is coupled to the first output terminal and the second output terminal to perform signal receiving through the mixer circuit. A control circuit adjusts the impedance of the variable load when a residual echo noise amount does not satisfy a minimum echo noise amount condition, and stops to adjust the impedance when the residual echo noise amount satisfies the condition.

Abstract: An echo estimation system includes a transceiver circuitry and a processor circuitry. The processor circuitry is coupled to the transceiver circuitry. The processor circuitry is configured to calculate linear echo power and non-linear echo power based on a signal under test in the transceiver circuitry. The linear echo power and the non-linear echo power are utilized to determine a quality of the transceiver circuitry or utilized to determine component parameters of the transceiver circuitry.

Abstract: The present disclosure discloses a signal equalization apparatus. A channel length estimation circuit determines a transmission channel length of the input signal such that a processing circuit retrieves predetermined feed-forward equalizer coefficients. A feed-forward equalizer equalizes the input signal according to operation feed-forward equalizer coefficients. An auto gain circuit amplifies the input signal according to an offset signal. A signal adding circuit adds the amplified input signal and a feedback adjusting signal to generate an added input signal. A data slicer generates a data-slicing result and the offset signal according to reference thresholds based on the added input signal. A feedback equalizer equalizes the data-slicing result to generate the feedback adjusting signal according to operation feedback equalizer coefficients.

Abstract: The present disclosure discloses a signal equalization apparatus. A channel length estimation circuit determines a transmission channel length of the input signal such that a processing circuit retrieves predetermined feed-forward equalizer coefficients. A feed-forward equalizer equalizes the input signal according to operation feed-forward equalizer coefficients. An auto gain circuit amplifies the input signal according to an offset signal. A signal adding circuit adds the amplified input signal and a feedback adjusting signal to generate an added input signal. A data slicer generates a data-slicing result and the offset signal according to reference thresholds based on the added input signal. A feedback equalizer equalizes the data-slicing result to generate the feedback adjusting signal according to operation feedback equalizer coefficients.

Abstract: A light-emitting device includes a substrate including an upper surface; a light-emitting stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the light-emitting stack includes a first surface and a second surface opposite to the first surface toward to the upper surface; a plurality of depressions formed in the light-emitting stack and penetrating the second semiconductor layer, the active layer and a portion of the first semiconductor layer; an insulative layer covering the second surface of the light-emitting stack; a connector including a first portion and a second portion; and an electrode disposed at a side of the light-emitting stack and electrically connecting the connector, wherein the first portion of the connector is formed in the plurality of depressions, the second portion of the connector is between the insulative layer and the light-emitting stack.

Abstract: A light-emitting device includes a substrate including an upper surface; a light-emitting stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the light-emitting stack includes a first surface and a second surface opposite to the first surface toward to the upper surface; a plurality of depressions formed in the light-emitting stack and penetrating the second semiconductor layer, the active layer and a portion of the first semiconductor layer; an insulative layer covering the second surface of the light-emitting stack; a connector including a first portion and a second portion; and an electrode disposed at a side of the light-emitting stack and electrically connecting the connector, wherein the first portion of the connector is formed in the plurality of depressions, the second portion of the connector is between the insulative layer and the light-emitting stack.

Abstract: This invention discloses a signal transmitting and receiving circuit of a digital subscriber line used for transmitting an output signal to a telecommunication loop or receiving an input signal from the telecommunication loop. The signal transmitting and receiving circuit comprises a transformer, which is coupled to the telecommunication loop; a signal transmitting module, which is coupled to the transformer, for generating the output signal; a signal receiving module, which is coupled to the transformer, for processing the input signal; an echo cancelling circuit, comprising passive components and having two ends, one of which is coupled to the signal transmitting module and the transformer, the other is coupled to the signal receiving module and the transformer. The output signal is transmitted to the telecommunication loop via the electromagnetic coupling of the transformer, and the input signal is received by the signal receiving module by the electromagnetic coupling of the transformer.

Abstract: A light-emitting device comprises: a conductive substrate; a conductive structure formed on the substrate, defining a first region and a second region laterally adjacent to the first region; a light-emitting structure formed on the first region; and a dielectric structure comprising a first dielectric layer and a second dielectric layer within the second region.

Abstract: The present invention discloses a transceiver of digital subscriber line (DSL) which supports a variety of DSL systems, comprising: a transmission circuit for receiving an output signal and generating a first DSL transmission signal or a second DSL transmission signal according to the output signal under the control of a transmission selection parameter; a hybrid circuit for generating a line transmission signal according to the first or second DSL transmission signal and generating a DSL reception signal according to a line reception signal; and a reception circuit for generating a first DSL reception signal or a second DSL reception signal according to the DSL reception signal, and then outputting one of the first and second DSL reception signals as an input signal according to a reception selection parameter.

Abstract: A method for manufacturing a light-emitting device comprising the steps of: providing a first substrate, a chip area, and a street area; forming a light-emitting structure on the first substrate; forming a conductive structure between the first substrate and the light-emitting structure; removing a part of the light-emitting structure in the street area to expose a sidewall of the light-emitting structure in the chip area; forming a first passivation layer on the light-emitting structure in the chip area; forming a second passivation layer on the conductive structure in the street area, on the sidewalls of the light-emitting structure, and on the sidewalls of the first passivation layer; forming a through-hole in the first passivation layer, and forming an electrode in the through-hole.

Abstract: The present disclosure provides a light-emitting device having a patterned interface composed of a plurality of predetermined patterned structures mutually distinct, wherein the plurality of predetermined patterned structures are repeatedly arranged in the patterned interface such that any two neighboring patterned structures are different from each other. The present disclosure also provides a manufacturing method of the light-emitting device. The method comprises the steps of providing a substrate, generating a random pattern arrangement by a computing simulation, forming a mask having the random pattern arrangement on the substrate, and removing a portion of the substrate thereby transferring the random pattern arrangement to the substrate.