Patents by Inventor Cheng-Hsien Li

Cheng-Hsien Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12211741
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Publication number: 20250016032
    Abstract: A signal processing device includes a proprietary test mode symbol generating circuit, a decision error detection circuit, and a debug control circuit. The proprietary test mode symbol generating circuit generates prediction symbols as a reference signal according to decision symbols output by a slicer of a receiving signal processing circuit and a predetermined rule. The decision error detection circuit operating in a proprietary test mode continues receiving the decision symbols and the prediction symbols, and generates detection results. The debug control circuit includes a memory device, and continues recording contents of one or more signals obtained from one or more nodes of the receiving signal processing circuit into the memory device. In addition, the debug control circuit receives the detection results, and stops recording the contents of the one or more signals in response to a state of at least one of the detection results.
    Type: Application
    Filed: July 3, 2024
    Publication date: January 9, 2025
    Applicant: Realtek Semiconductor Corp.
    Inventors: Tsung-En Wu, Cheng-Hsien Li, Hua-Lun Pi
  • Publication number: 20240395986
    Abstract: A light-emitting element, a manufacturing method thereof, and a package structure are provided. The light-emitting element includes a first semiconductor layer, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, and a convex lens structure disposed on the second semiconductor layer. The convex lens structure includes a plurality of microlenses. The microlenses and the second semiconductor layer are integrally formed and have the same material. The radius of curvature of one of the microlenses is 0.2 ?m to 5.0 ?m, and the light-emission angle of the light-emitting element is 100° to 110°.
    Type: Application
    Filed: May 20, 2024
    Publication date: November 28, 2024
    Inventors: Shiou-Yi KUO, Jian-Chin LIANG, Cheng-Hsien LI, Kai Hung CHENG
  • Publication number: 20240355986
    Abstract: A micro light-emitting diode package structure and a forming method thereof are provided. The micro light-emitting diode package structure includes micro light-emitting diode dies, a light-transmitting layer, a first insulating layer, redistribution layers, and conductive elements. The micro light-emitting diode dies are disposed side by side and each includes an electrode surface, a light-emitting surface, and side surfaces. The electrode surface and the light-emitting surface are opposite to each other, and the side surfaces are between them. The light-transmitting layer covers the light-emitting surface and the side surfaces. The first insulating layer is under the micro light-emitting diode dies and in direct contact with the electrode surface. The redistribution layers are disposed under the first insulating layer and pass through the first insulating layer to electrically connect the electrode surface.
    Type: Application
    Filed: April 11, 2024
    Publication date: October 24, 2024
    Inventors: Shiou-Yi KUO, Guo-Yi SHIU, Chin-Hung LO, Chih-Hao LIN, Cheng-Hsien LI, Wei-Yuan MA
  • Publication number: 20240119916
    Abstract: An electronic device includes an application processor and a display control circuit. The display control circuit may output a (tearing effect) TE signal to the application processor and receive an image frame from the application processor. A data processing circuit of the display control circuit generates a notification signal when the data processing circuit is ready to receive the image frame from the application processor. The timing controller generates the TE signal having a first frequency during a period from a first time point when the notification signal is received to a second time point when the application processor starts transmitting the image frame to the data processing circuit. The first frequency is greater than a reference frequency based on an output frame rate of the display control circuit.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Cheng Hsien Li, Yuan-Po Cheng
  • Patent number: 11948535
    Abstract: An electronic device includes an application processor and a display control circuit. The display control circuit may output a (tearing effect) TE signal to the application processor and receive an image frame from the application processor. A data processing circuit of the display control circuit generates a notification signal when the data processing circuit is ready to receive the image frame from the application processor. The timing controller generates the TE signal having a first frequency during a period from a first time point when the notification signal is received to a second time point when the application processor starts transmitting the image frame to the data processing circuit. The first frequency is greater than a reference frequency based on an output frame rate of the display control circuit.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: April 2, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Cheng Hsien Li, Yuan-Po Cheng
  • Publication number: 20240080173
    Abstract: An electronic device includes a processor circuit, a frequency-domain-to-time-domain conversion circuit, a transmitter circuit, a hybrid circuit, a receiver circuit, and a time-domain-to-frequency-domain conversion circuit. The processor circuit generates a frequency-domain transmitting signal. The frequency-domain-to-time-domain conversion circuit converts the frequency-domain transmitting signal into a first time-domain transmitting signal. The transmitter circuit generates a second time-domain transmitting signal. The hybrid circuit includes an echo noise cancelling path and an echo noise path. When the echo noise cancelling path is turned off, the processor circuit receives a first frequency-domain receiving signal. When the echo noise cancelling path is turned on, the processor circuit receives a second frequency-domain receiving signal.
    Type: Application
    Filed: June 27, 2023
    Publication date: March 7, 2024
    Inventors: Cheng-Hsien LI, Bo-Rong HUANG
  • Patent number: 11711111
    Abstract: The present invention discloses a signal transceiving apparatus having echo-canceling mechanism. A mixer circuit includes a Wheatstone bridge and a transformer winding circuit. The Wheatstone bridge includes another transformer winding circuit and a variable load and includes a first input terminal, a first output terminal, a second input terminal and a second output terminal located at each two neighboring arms in an order. A transmission circuit is coupled to the first input terminal and the second input terminal to perform signal transmission through the mixer circuit. A receiving circuit is coupled to the first output terminal and the second output terminal to perform signal receiving through the mixer circuit. A control circuit adjusts the impedance of the variable load when a residual echo noise amount does not satisfy a minimum echo noise amount condition, and stops to adjust the impedance when the residual echo noise amount satisfies the condition.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: July 25, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Cheng-Hsien Li
  • Publication number: 20230188102
    Abstract: An amplifier circuit includes a continuous-time linear equalizer, an adjustable gain circuit and a filter circuit. The continuous-time linear equalizer includes a first high-pass path, a first low-pass path, a second high-pass path, and a second low-pass path. The first high-pass path is used to increase a gain of a high-frequency part of a first signal source, and the second high-pass path is used to increase a gain of a high-frequency part of a second signal source. The filter circuit is used to amplify and filter the first signal source and the second signal source, and includes a fully-differential operational amplifier, a first filter network, and a second filter network.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 15, 2023
    Inventors: CHIA-WEI YU, YUNG-TAI CHEN, TSUNG-EN WU, CHENG-HSIEN LI, SHENG-YANG HO
  • Patent number: 11558126
    Abstract: An echo estimation system includes a transceiver circuitry and a processor circuitry. The processor circuitry is coupled to the transceiver circuitry. The processor circuitry is configured to calculate linear echo power and non-linear echo power based on a signal under test in the transceiver circuitry. The linear echo power and the non-linear echo power are utilized to determine a quality of the transceiver circuitry or utilized to determine component parameters of the transceiver circuitry.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: January 17, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Bo-Rong Huang, Cheng-Hsien Li, Tsung-En Wu, Yu-Tung Liao
  • Publication number: 20220200657
    Abstract: The present invention discloses a signal transceiving apparatus having echo-canceling mechanism. A mixer circuit includes a Wheatstone bridge and a transformer winding circuit. The Wheatstone bridge includes another transformer winding circuit and a variable load and includes a first input terminal, a first output terminal, a second input terminal and a second output terminal located at each two neighboring arms in an order. A transmission circuit is coupled to the first input terminal and the second input terminal to perform signal transmission through the mixer circuit. A receiving circuit is coupled to the first output terminal and the second output terminal to perform signal receiving through the mixer circuit. A control circuit adjusts the impedance of the variable load when a residual echo noise amount does not satisfy a minimum echo noise amount condition, and stops to adjust the impedance when the residual echo noise amount satisfies the condition.
    Type: Application
    Filed: June 25, 2021
    Publication date: June 23, 2022
    Inventor: CHENG-HSIEN LI
  • Publication number: 20220014281
    Abstract: An echo estimation system includes a transceiver circuitry and a processor circuitry. The processor circuitry is coupled to the transceiver circuitry. The processor circuitry is configured to calculate linear echo power and non-linear echo power based on a signal under test in the transceiver circuitry. The linear echo power and the non-linear echo power are utilized to determine a quality of the transceiver circuitry or utilized to determine component parameters of the transceiver circuitry.
    Type: Application
    Filed: May 28, 2021
    Publication date: January 13, 2022
    Inventors: Bo-Rong HUANG, Cheng-Hsien LI, Tsung-En WU, Yu-Tung LIAO
  • Patent number: 11206159
    Abstract: The present disclosure discloses a signal equalization apparatus. A channel length estimation circuit determines a transmission channel length of the input signal such that a processing circuit retrieves predetermined feed-forward equalizer coefficients. A feed-forward equalizer equalizes the input signal according to operation feed-forward equalizer coefficients. An auto gain circuit amplifies the input signal according to an offset signal. A signal adding circuit adds the amplified input signal and a feedback adjusting signal to generate an added input signal. A data slicer generates a data-slicing result and the offset signal according to reference thresholds based on the added input signal. A feedback equalizer equalizes the data-slicing result to generate the feedback adjusting signal according to operation feedback equalizer coefficients.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: December 21, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Tsung-En Wu, Cheng-Hsien Li
  • Publication number: 20210144030
    Abstract: The present disclosure discloses a signal equalization apparatus. A channel length estimation circuit determines a transmission channel length of the input signal such that a processing circuit retrieves predetermined feed-forward equalizer coefficients. A feed-forward equalizer equalizes the input signal according to operation feed-forward equalizer coefficients. An auto gain circuit amplifies the input signal according to an offset signal. A signal adding circuit adds the amplified input signal and a feedback adjusting signal to generate an added input signal. A data slicer generates a data-slicing result and the offset signal according to reference thresholds based on the added input signal. A feedback equalizer equalizes the data-slicing result to generate the feedback adjusting signal according to operation feedback equalizer coefficients.
    Type: Application
    Filed: November 4, 2020
    Publication date: May 13, 2021
    Inventors: TSUNG-EN WU, CHENG-HSIEN LI
  • Patent number: 10297718
    Abstract: A light-emitting device includes a substrate including an upper surface; a light-emitting stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the light-emitting stack includes a first surface and a second surface opposite to the first surface toward to the upper surface; a plurality of depressions formed in the light-emitting stack and penetrating the second semiconductor layer, the active layer and a portion of the first semiconductor layer; an insulative layer covering the second surface of the light-emitting stack; a connector including a first portion and a second portion; and an electrode disposed at a side of the light-emitting stack and electrically connecting the connector, wherein the first portion of the connector is formed in the plurality of depressions, the second portion of the connector is between the insulative layer and the light-emitting stack.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: May 21, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Wei-Jung Chung, Jennhwa Fu, Cheng-Hsien Li, Chi-Hao Huang
  • Publication number: 20170033265
    Abstract: A light-emitting device includes a substrate including an upper surface; a light-emitting stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the light-emitting stack includes a first surface and a second surface opposite to the first surface toward to the upper surface; a plurality of depressions formed in the light-emitting stack and penetrating the second semiconductor layer, the active layer and a portion of the first semiconductor layer; an insulative layer covering the second surface of the light-emitting stack; a connector including a first portion and a second portion; and an electrode disposed at a side of the light-emitting stack and electrically connecting the connector, wherein the first portion of the connector is formed in the plurality of depressions, the second portion of the connector is between the insulative layer and the light-emitting stack.
    Type: Application
    Filed: October 14, 2016
    Publication date: February 2, 2017
    Inventors: Wei-Jung CHUNG, Jennhwa FU, Cheng-Hsien LI, Chi-Hao HUANG
  • Patent number: 9312912
    Abstract: This invention discloses a signal transmitting and receiving circuit of a digital subscriber line used for transmitting an output signal to a telecommunication loop or receiving an input signal from the telecommunication loop. The signal transmitting and receiving circuit comprises a transformer, which is coupled to the telecommunication loop; a signal transmitting module, which is coupled to the transformer, for generating the output signal; a signal receiving module, which is coupled to the transformer, for processing the input signal; an echo cancelling circuit, comprising passive components and having two ends, one of which is coupled to the signal transmitting module and the transformer, the other is coupled to the signal receiving module and the transformer. The output signal is transmitted to the telecommunication loop via the electromagnetic coupling of the transformer, and the input signal is received by the signal receiving module by the electromagnetic coupling of the transformer.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: April 12, 2016
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yung-Tai Chen, Cheng-Hsien Li, Hung-Chen Chu, Jian-Ru Lin
  • Publication number: 20150311400
    Abstract: A light-emitting device comprises: a conductive substrate; a conductive structure formed on the substrate, defining a first region and a second region laterally adjacent to the first region; a light-emitting structure formed on the first region; and a dielectric structure comprising a first dielectric layer and a second dielectric layer within the second region.
    Type: Application
    Filed: July 7, 2015
    Publication date: October 29, 2015
    Inventors: Cheng-Hsien LI, Chi-Hao HUANG, Hsin-Hsiung HUANG
  • Patent number: 9083427
    Abstract: The present invention discloses a transceiver of digital subscriber line (DSL) which supports a variety of DSL systems, comprising: a transmission circuit for receiving an output signal and generating a first DSL transmission signal or a second DSL transmission signal according to the output signal under the control of a transmission selection parameter; a hybrid circuit for generating a line transmission signal according to the first or second DSL transmission signal and generating a DSL reception signal according to a line reception signal; and a reception circuit for generating a first DSL reception signal or a second DSL reception signal according to the DSL reception signal, and then outputting one of the first and second DSL reception signals as an input signal according to a reception selection parameter.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: July 14, 2015
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Cheng-Hsien Li
  • Patent number: 9076923
    Abstract: A method for manufacturing a light-emitting device comprising the steps of: providing a first substrate, a chip area, and a street area; forming a light-emitting structure on the first substrate; forming a conductive structure between the first substrate and the light-emitting structure; removing a part of the light-emitting structure in the street area to expose a sidewall of the light-emitting structure in the chip area; forming a first passivation layer on the light-emitting structure in the chip area; forming a second passivation layer on the conductive structure in the street area, on the sidewalls of the light-emitting structure, and on the sidewalls of the first passivation layer; forming a through-hole in the first passivation layer, and forming an electrode in the through-hole.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: July 7, 2015
    Assignee: EPISTAR CORPORATION
    Inventors: Cheng-Hsien Li, Chi-Hao Huang, Hsin-Hsiung Huang