Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.

Abstract: Provided herein are methods and compositions for oligonucleotide synthesis utilizing universal linker phosphoramidites. Methods and reagents are described with DNA synthesis using controlled pore glass (CPG) solid supports, and on platinum coated electrodes for electrochemical DNA synthesis. The universal linkers can be used as spacers in single-column PCR primer synthesis to generate 2 strands with free 3?-hydroxy termini after cleavage. The methods and compositions utilize a solid support system for synthesis of oligonucleotides, wherein the support has platinum electrodes and a universal linker, optionally wherein the platinum electrode is coated with an amine. The methods and compositions further describe use of universal linker phosphoramidites and the platinum electrode is coated with a monosaccharide, or a disaccharide.

Abstract: A primer group and method for detecting single-base mutations. The primer group comprises the following primers: an identification primer, which is composed of, from the 5? end to the 3? end, (a) a nucleotide sequence which complements a segment of continuous nucleotides in a nucleic acid sequence to be detected, wherein the 5? end of the continuous nucleotides starts at a first nucleotide downstream of an expected mutation site; and (b) a nucleotide which complements a non-mutated nucleotide or an expected mutated nucleotide at the expected single-base mutation site of the nucleic acid sequence. The primer group also comprises an amplification primer. The amplification primer is capable of using the identification primer to amplify an amplification product which is obtained by amplifying the nucleic acid sequence. The identification primer is 1 to 19 nucleotides less than the amplification primer.

Abstract: A method includes applying a first voltage pulse across a memory cell, wherein the memory cell includes a selector, wherein the first voltage pulse switches the selector into an on-state; after applying the first voltage pulse, applying a second voltage pulse across the memory cell, wherein before applying the second voltage pulse the selector has a first voltage threshold, wherein after applying the second voltage pulse the selector has a second voltage threshold that is less than the first voltage threshold; and after applying the second voltage pulse, applying a third voltage pulse across the memory cell, wherein the third voltage pulse switches the selector into an on-state; wherein the selector remains continuously in an off-state between the first voltage pulse and the third voltage pulse.

Abstract: A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.

Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.

Abstract: Embodiments include a Schottky barrier diode (SBD) structure and method of forming the same, the SBD structure including a current blockage feature to inhibit current from leaking at an interface with a shallow trench isolation regions surrounding an anode region of the SBD structure.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes depositing a germanium layer over a silicon substrate; forming an oxide capping layer over the germanium layer; after forming the oxide capping layer, annealing the germanium layer to diffuse germanium atoms of the germanium layer into the silicon substrate, such that a portion of the silicon substrate is turned into a silicon germanium layer; and forming a gate structure over the silicon germanium layer.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: An operation method for a memory device is provided. The memory device includes a two-terminal selector and a resistance variable storage element coupled to the two-terminal selector. The method includes providing a voltage pulse to the memory device. A voltage applied across the two-terminal selector during a falling part of the voltage pulse falls below a holding voltage of the two-terminal selector. A voltage falling rate of the falling part at which the voltage applied across the two-terminal selector reaches the holding voltage is raised for reducing threshold voltage drift of the two-terminal selector.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a gate structure, and a source/drain feature. The semiconductor substrate includes a semiconductor fin, wherein the semiconductor fin comprises a silicon germanium portion. The isolation structure is at a sidewall of a bottom portion of the silicon germanium portion. A top portion of the silicon germanium portion is higher than a top surface of the isolation structure, and an atomic concentration of germanium in the top portion of the silicon germanium portion is greater than an atomic concentration of germanium in the bottom portion of the silicon germanium portion. The gate structure is over a first portion of the silicon germanium portion of the semiconductor fin. The source/drain feature is over a second portion of the silicon germanium portion of the semiconductor fin.

Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.

Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Abstract: A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: A method for in vitro transcription of a DNA template into RNA includes providing a mixture containing a buffer substance, ribonucleoside triphosphates (NTPs), one or more magnesium salts in a concentration of from about 2 mM to about 60 mM, the DNA template, and a recombinant RNA polymerase, and incubating the reaction mixture at from about 25° C. to about 40° C. for from about 1 hour to about 12 hours thereby producing the RNA. A method for in vitro transcription includes providing a DNA template and a cap analogue that binds to ?1 and/or +1 nucleotides of promoter for in vitro transcription, thus producing more full length mRNAs, allowing for more flexibility on the choice of first mRNA base, and providing +2 position open for custom sequence.

Abstract: A method for in vitro transcription of a DNA template into RNA includes providing a mixture containing a buffer substance, ribonucleoside triphosphates (NTPs), one or more magnesium salts in a concentration of from about 2 mM to about 60 mM, the DNA template, and a recombinant RNA polymerase, and incubating the reaction mixture at from about 25° C. to about 40° C. for from about 1 hour to about 12 hours thereby producing the RNA. A method for in vitro transcription includes providing a DNA template and a cap analogue that binds to ?1 and/or +1 nucleotides of promoter for in vitro transcription, thus producing more full length mRNAs, allowing for more flexibility on the choice of first mRNA base, and providing +2 position open for custom sequence.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.

Abstract: A memory device includes a substrate, a bottom electrode disposed over the substrate, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer. The selector layer is an oxygen-doped chalcogenide based film, and an oxygen content of the selector layer is about 10 at % or less.

Abstract: A device includes a channel layer, a gate structure, a first gate spacer, and a second gate spacer. The gate structure wraps around the channel layer. The first gate spacer and the second gate spacer are on opposite sides of the gate structure. The first gate spacer has a first portion and a second portion between the gate structure and the first portion of the first gate spacer, and a dopant concentration of the second portion of the first gate spacer is greater than a dopant concentration of the first portion of the first gate spacer.