Abstract: A device includes a channel layer, a gate structure, a first gate spacer, and a second gate spacer. The gate structure wraps around the channel layer. The first gate spacer and the second gate spacer are on opposite sides of the gate structure. The first gate spacer has a first portion and a second portion between the gate structure and the first portion of the first gate spacer, and a dopant concentration of the second portion of the first gate spacer is greater than a dopant concentration of the first portion of the first gate spacer.

Abstract: A memory device includes a spin-orbit torque (“SOT”) conductor, a magnetic tunneling junction (“MTJ”) structure above the SOT conductor, a two-terminal read selector above the MTJ structure, a two-terminal write selector above the MTJ structure, and a bit line below the SOT conductor. The two-terminal read selector is conductively connected to the pinned layer in the MTJ structure. The two-terminal write selector is conductively connected to a first terminal of the SOT conductor. The bit line is conductively connected to a second terminal of the SOT conductor.

Abstract: A method of fabricating a semiconductor structure provided herein includes providing a thick-metal density range for a model structure, wherein the model structure includes a wafer substrate, and layers of metal patterns stacking on the wafer substrate; modifying the thick-metal density range to constrain a warpage range of the model structure toward a target range of warpage; and fabricating the semiconductor structure by forming the layers of metal patterns on the wafer substrate, wherein a thick-metal layer among the layers of metal patterns is formed based on the modified thick-metal density range, and a thickness of the thick-metal layer is twice or more of a thickness of one of the layers of metal patterns next to the thick-metal layer. A semiconductor structure fabricating by using the above method is further provided.

Abstract: An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.

Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.

Abstract: A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, a gate conductive structure over the gate dielectric layer, and a first insulating spacer alongside the gate conductive structure and over the plurality of nanostructures. The first insulating spacer is in direct contact with the gate conductive structure and the gate dielectric layer.

Abstract: A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.

Abstract: A method for in vitro transcription of a DNA template into RNA includes providing a mixture containing a buffer substance, ribonucleoside triphosphates (NTPs), one or more magnesium salts in a concentration of from about 2 mM to about 60 mM, the DNA template, and a recombinant RNA polymerase, and incubating the reaction mixture at from about 25° C. to about 40° C. for from about 1 hour to about 12 hours thereby producing the RNA. A method for in vitro transcription includes providing a DNA template and a cap analogue that binds to ?1 and/or +1 nucleotides of promoter for in vitro transcription, thus producing more full length mRNAs, allowing for more flexibility on the choice of first mRNA base, and providing+2 position open for custom sequence.

Abstract: Provided are a primer set and a gene chip method for detecting a single base mutation, wherein the gene chip method comprises: providing a sample containing a nucleic acid sequence to be detected; amplifying the nucleic acid sequence to be detected in the sample by using a primer set by means of a polymerase chain reaction, and purifying the amplification product obtained after the polymerase chain reaction to remove unreacted primers and enzymes; and hybridizing the purified amplification product with a chip probe, and detecting mutation information of the nucleic acid sequence to be detected by using a chip reader. According to the method, a target nucleic acid sequence is amplified while a base mutation site is identified, which not only achieves the enhanced sensitivity of detection, but also can achieve simultaneous and rapid detection of multiple target nucleic acid sequences on the basis of the characteristics of a high-throughput dot matrix of a chip, high reading speed, etc.

Abstract: A method for synthesizing single-stranded DNA, specifically a process for producing single-stranded DNA without base mutations, is provided, by which single-stranded DNA is produced by uracil-specific excision reagent (USER)-mediated self-looping of double-stranded DNA combined with rolling circle replication.

Abstract: A control method to operate a memory device, a control method to operate a memory system and a control system are provided. The control method includes providing a first voltage to a memory device for accessing a memory element of the memory device; obtaining an aging information of the memory device; and providing a second voltage to the memory device according to the aging information, wherein the first voltage and the second voltage are reverse biased voltages.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: A memory system and an operating method are provided. The memory system comprises a memory array, a control circuit, and a read circuit. The memory array comprises a plurality of cross-point memory cells, and each cross-point memory cell comprises a selector and a memory element coupled in series between both terminals of the cross-point memory cell. The control circuit is coupled to the memory array, and the control circuit is configured to provide at least one read pulse each with an increasing magnitude to a selected cross-point memory cell. The read circuit is coupled to the memory array, and the read circuit is configured to receive a read current flowing through the selected cross-point memory cell and determines whether the read current is greater than a target current.

Abstract: Operating method, memory system, and control circuit are provided. The operating method is for operating a memory device comprising a selector and a memory element serially coupled to the selector. The operating method comprises presetting the memory device by providing a preset signal to the memory device, wherein the preset signal is clamped at a first current; and accessing the memory device by providing an access signal to the memory device, wherein a second current greater than the first current flows through the memory device when the access signal is provided to the memory device.

Abstract: A method of preparing a circular RNA includes transcribing a vector to form a precursor RNA, in which the vector includes the following elements operably connected to each other and arranged in the following sequence: a) a 5? element, b) a 3? Group I self-splicing intron fragment containing a 3? splice site dinucleotide, c) none or an element containing an internal ribosome entry site (IRES) and a protein coding region or an element containing a noncoding region, d) a 5? Group I self-splicing intron fragment containing a 5? splice site dinucleotide, and e) a 3? element, in which the 5? element and the 3? element form a stable structure with a Gibbs free energy (?G) from ?190 kcal/mol to ?9.0 kcal/mol, provided that the stable structure is not a duplex with at least 95% base pairing between the 5? element and the 3? element, in which the 3? Group I self-splicing intron fragment and the 5? Group I self-splicing intron fragment form a self-cleaving and self-ligating RNA molecule, thereby generating circular RNA.

Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.

Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.

Abstract: A method includes applying a first voltage pulse across a memory cell, wherein the memory cell includes a selector, wherein the first voltage pulse switches the selector into an on-state; after applying the first voltage pulse, applying a second voltage pulse across the memory cell, wherein before applying the second voltage pulse the selector has a first voltage threshold, wherein after applying the second voltage pulse the selector has a second voltage threshold that is less than the first voltage threshold; and after applying the second voltage pulse, applying a third voltage pulse across the memory cell, wherein the third voltage pulse switches the selector into an on-state; wherein the selector remains continuously in an off-state between the first voltage pulse and the third voltage pulse.

Abstract: Functionalized aryldiazonium salts and films formed by electrografting of functionalized aryldiazonium salts are provided. Methods for purifying functionalized aryldiazonium salts and for coating solid support systems with functionalized aryldiazonium salts are also provided. These coated solid support systems can be used, for example, in methods of oligonucleotide synthesis.

Abstract: A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.