Patents by Inventor Cheng-Hsien Wu
Cheng-Hsien Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11898186Abstract: A method for in vitro transcription of a DNA template into RNA includes providing a mixture containing a buffer substance, ribonucleoside triphosphates (NTPs), one or more magnesium salts in a concentration of from about 2 mM to about 60 mM, the DNA template, and a recombinant RNA polymerase, and incubating the reaction mixture at from about 25° C. to about 40° C. for from about 1 hour to about 12 hours thereby producing the RNA. A method for in vitro transcription includes providing a DNA template and a cap analogue that binds to ?1 and/or +1 nucleotides of promoter for in vitro transcription, thus producing more full length mRNAs, allowing for more flexibility on the choice of first mRNA base, and providing +2 position open for custom sequence.Type: GrantFiled: December 20, 2022Date of Patent: February 13, 2024Assignee: GENSCRIPT USA INC.Inventors: Cheng-Hsien Wu, Fengmei Pi, Robert Dempcy, Shambhavi Shubham, Kristine Bielecki, Aaron Ball
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Patent number: 11894263Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.Type: GrantFiled: October 7, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hsien Wu, Chung-Yi Lin, Yen-Sen Wang
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Publication number: 20240040802Abstract: A memory device includes a substrate, a bottom electrode disposed over the substrate, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer. The selector layer is an oxygen-doped chalcogenide based film, and an oxygen content of the selector layer is about 10 at % or less.Type: ApplicationFiled: January 11, 2023Publication date: February 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsien Wu, Chen-Feng Hsu, Chien-Min Lee, Tung-Ying Lee, Xinyu BAO, Elia Ambrosi, Hengyuan Lee
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Publication number: 20240014294Abstract: A device includes a channel layer, a gate structure, a first gate spacer, and a second gate spacer. The gate structure wraps around the channel layer. The first gate spacer and the second gate spacer are on opposite sides of the gate structure. The first gate spacer has a first portion and a second portion between the gate structure and the first portion of the first gate spacer, and a dopant concentration of the second portion of the first gate spacer is greater than a dopant concentration of the first portion of the first gate spacer.Type: ApplicationFiled: September 21, 2023Publication date: January 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Cheng-Hsien WU
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Publication number: 20240015988Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.Type: ApplicationFiled: September 22, 2023Publication date: January 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Xinyu BAO, Hengyuan Lee, Ying-Yu Chen
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Patent number: 11862732Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a first fin, and the first fin has a channel region and a source/drain region. The method includes forming a stack structure over the first fin, and the stack structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over the fin. The method also includes removing a portion of the second semiconductor layer in the channel region, and a portion of the first semiconductor layer is remaining in the channel region. The method further includes forming a cladding layer over the remaining first semiconductor material layer in the channel region to form a nanostructure, wherein the nanostructure has a dumbbell shape. The method includes forming a gate structure surrounding the nanostructure.Type: GrantFiled: August 30, 2021Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wilman Tsai, Cheng-Hsien Wu, I-Sheng Chen, Stefan Rusu
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Publication number: 20230422518Abstract: A memory device is provided. The memory device includes memory cells. Each of the memory cells includes: a resistance variable storage device; and a selector. The selector is stacked with the resistance variable storage device and coupled to the resistance variable storage device with a shared terminal, and includes a switching layer formed of a chalcogenide compound. A thickness of the switching layer is equal to or less than about 5 nm.Type: ApplicationFiled: January 9, 2023Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Elia Ambrosi, Xinyu BAO, Cheng-Hsien Wu
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Patent number: 11855151Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.Type: GrantFiled: June 21, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Sheng Chen, Cheng-Hsien Wu, Chih Chieh Yeh, Yee-Chia Yeo
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Publication number: 20230386856Abstract: A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventor: Cheng-Hsien WU
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Publication number: 20230386573Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.Type: ApplicationFiled: May 27, 2022Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Elia Ambrosi, Cheng-Hsien Wu, Hengyuan Lee, Chien-Min Lee, Xinyu BAO
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Publication number: 20230386899Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Cheng-Hsien Wu, Chung-Yi Lin, Yen-Sen Wang
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Patent number: 11830927Abstract: A method includes: forming a dummy gate dielectric layer over a channel region of a fin structure; forming a dummy gate over the dummy gate dielectric layer; removing the dummy gate and a first portion of the dummy gate dielectric layer to expose the channel region of the fin structure; removing a first nanowire of the fin structure above a second nanowire of the fin structure to remain the second nanowire of the fin structure; forming an interfacial layer surrounding the second nanowire; forming a material layer comprising dopants over the interfacial layer; and performing an annealing process to drive the dopants of the material layer into the interfacial layer, thereby forming a doped interfacial layer surrounding the second nanowire.Type: GrantFiled: January 13, 2022Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Cheng-Hsien Wu
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Publication number: 20230371280Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufactruring Company, Ltd.Inventors: Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Xinyu Bao, Hengyuan Lee, Ying-Yu Chen
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Publication number: 20230371279Abstract: Embodiments include a method of forming a cross-point memory device, the method and device forming a multi-layered selector material. A first level of the multi-layered selector structure may include a subset of the elements of a second level of the multi-tiered selector structure. A gradient concentration of the switching elements may be found in the selector structure, first level including a substantially steady concentration of elements and the second level including a gradient of concentration for the elements in common as well as the elements unique to the first level.Type: ApplicationFiled: August 16, 2022Publication date: November 16, 2023Inventors: Cheng-Hsien Wu, Xinyu Bao, Elia Ambrosi
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Publication number: 20230348894Abstract: Provided is a large-storage capacity gene mutation library construction method, capable of synthesizing relatively few oligomer sequences, then assembling same to create a large-storage capacity gene mutation library.Type: ApplicationFiled: December 18, 2020Publication date: November 2, 2023Inventors: Xiaohui Dai, Yifan Li, Cheng-Hsien Wu
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Patent number: 11805661Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.Type: GrantFiled: April 27, 2021Date of Patent: October 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Xinyu Bao, Hengyuan Lee, Ying-Yu Chen
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Publication number: 20230332134Abstract: Provided is an automated system for preparing purified plasmid DNA in commercial scale.Type: ApplicationFiled: August 17, 2021Publication date: October 19, 2023Applicants: Nanjing GenScript Biotech Co., Ltd., GenScript USA Inc.Inventors: Stephen Richard Hughes, Xiaoli Fu, Yifan Li, Yuzhuo He, Hong Li, Cheng-Hsien Wu, Chuan Sun
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Patent number: 11753667Abstract: The present invention is directed to methods and materials for RNA-mediated gene assembly from oligonucleotide sequences. In some embodiments, the oligonucleotides used for gene assembly are provided in an array format. An RNA polymerase promoter is appended to surface-bound oligonucleotides and a plurality of RNA copies of each oligonucleotide are then produced with an RNA polymerase. These RNA molecules self-assemble into a desired full-length RNA transcript by hybridization and ligation. The resulting RNA transcript may then be converted into double stand DNA useful in a variety of applications including protein expression.Type: GrantFiled: December 12, 2017Date of Patent: September 12, 2023Assignee: Wisconsin Alumni Research FoundationInventors: Cheng-Hsien Wu, Lloyd Smith
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Patent number: 11749526Abstract: A semiconductor substrate includes a first material layer made of a first material and including a plurality of protrusions, and a second material layer made of a second material different from the first material, filling spaces between the plurality of protrusions, and covering the plurality of protrusions. Each of the protrusions includes a tip and a plurality of facets converging at the tip, and adjacent facets of adjacent protrusions are in contact with each other.Type: GrantFiled: July 25, 2022Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu
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Patent number: 11742213Abstract: A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.Type: GrantFiled: November 13, 2020Date of Patent: August 29, 2023Inventor: Cheng-Hsien Wu