Patents by Inventor Cheng Hsin Chen

Cheng Hsin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11976124
    Abstract: The present disclosure provides isolated monoclonal antibodies or an antigen-binding portion thereof that specifically bind to CD40 preferably human CD40 with high affinity, and that function as CD40 agonists. The disclosed invention also relates to antibodies that are chimeric, humanized, bispecific, derivatized, single chain antibodies or portions of fusion proteins. Nucleic acid molecules encoding the antibodies of the disclosed invention, hybridoma, and methods for expressing the antibodies of the disclosed invention are also provided. Pharmaceutical compositions comprising the antibodies of the disclosed invention are also provided. This disclosure also provides methods for regulating humoral and cellular immune responses, as well as methods for treating cancer using an anti-CD40 agonist antibody of the disclosed invention.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 7, 2024
    Assignee: ABVISION, INC.
    Inventors: Chang-Hsin Chen, Gloria Zhang, Guochen Yan, Cheng-Chi Chao
  • Patent number: 11951091
    Abstract: Disclosed herein is a complex, a contrast agent and the method for treating a disease related to CXCR4 receptor. The complex is configured to bind the CXCR4 receptor, and is used as a medicament for diagnosis and treatment of cancers and other indications related to the CXCR4 receptor.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: April 9, 2024
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN, R.O.C
    Inventors: Chien-Chung Hsia, Chung-Hsin Yeh, Cheng-Liang Peng, Chun-Tang Chen
  • Publication number: 20240096498
    Abstract: A method for evaluating a risk of a subject getting a specific disease includes steps of: storing a reference database that contains original parameter sets; selecting target alleles from an SNP profile derived from genome sequencing data of a subject; selecting target parameter sets from among the original parameter sets; calculating, for each of the target parameter sets, a race factor based on a global risk allele frequency and a group-specific risk allele frequency included in the target parameter set; calculating a genetic factor based on statistics, global reference allele frequencies, the race factors for the target parameter sets, and numbers of chromosomes in homologous chromosome pairs included in the target parameter sets; calculating a citation factor based on numbers of citation times included in the target parameter sets; and calculating a risk score based on the genetic factor and the citation factor.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 21, 2024
    Inventors: Yi-Ting CHEN, Sing-Han HUANG, Ching-Yung LIN, Xiang-Yu LIN, Cheng-Tang WANG, Raksha NANDANAHOSUR RAMESH, Pei-Hsin CHEN
  • Publication number: 20240084012
    Abstract: An isolated bispecific antibody or antigen-binding portion thereof includes a first chain which specifically binds to human PD-1(hPD-1) and blocks the interaction between hPD-1 and PD-L1, and a second chain which specifically binds to human CD47 and inhibits its interaction with SIRP-alpha, where the first chain and the second chain are coupled in a knob-in-hole format through their respective CH3 domain.
    Type: Application
    Filed: December 31, 2021
    Publication date: March 14, 2024
    Inventors: Chun-Jen LIN, Cheng-Chi CHAO, Chang-Hsin Chen, Gloria Guohong ZHANG, Guochen YAN
  • Publication number: 20220392799
    Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 8, 2022
    Inventors: Chung-Lei CHEN, Cheng-Hsin CHEN, Chung Chieh TING, Che-Yi LIN, Clark LEE
  • Patent number: 11443976
    Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Lei Chen, Cheng-Hsin Chen, Chung Chieh Ting, Che-Yi Lin, Clark Lee
  • Patent number: 11375832
    Abstract: According to an example of the present disclosure, a learning tableware set includes a bowl and a spoon used in cooperation with the bowl. The bowl includes a bowl bottom and a curved bowl wall. The bowl bottom includes a peripheral recessed portion on one side of the bowl bottom. One side of the curved bowl wall is annularly connected to an edge of the side of the bowl bottom, and the other side of the curved bowl wall, which is not connected to the bowl bottom, includes a protruding edge extending toward a central axis of the bowl bottom. The spoon includes a holding portion and a scooping portion connected to the holding portion, and a curve of one end of the scooping portion away from the holding portion matches a curve of the peripheral recessed portion.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: July 5, 2022
    Assignee: CHANG YANG MATERIAL CORP.
    Inventors: Ming-Hua Huang, Lung-Hsun Song, Cheng-Hsin Chen, Lin-Chun Sun, Jian-Syun Lu
  • Publication number: 20220122880
    Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Chung-Lei CHEN, Cheng-Hsin CHEN, Chung Chieh TING, Che-Yi LIN, Clark LEE
  • Patent number: 11263106
    Abstract: A trace configuration calculating method is applied to pivotal connection of a first workpiece and a hinge. A first trace space is formed at a position where the hinge is pivoted to the first workpiece. A first trace is disposed through the first trace space. The trace configuration calculating method includes the hinge and the first workpiece rotating first and second angles to make the first trace space have first and second contour cross-sections respectively, overlapping the first and second contour cross-sections to form a first intersection area, calculating a first maximum inscribed circle according to the first intersection area, and determining a first optimal center and a first maximum diameter of the first trace according to the first maximum inscribed circle.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: March 1, 2022
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventors: Cheng-Hsin Chen, Chun-Hung Lin, Chun-Chieh Chen
  • Publication number: 20210386224
    Abstract: According to an example of the present disclosure, a learning tableware set includes a bowl and a spoon used in cooperation with the bowl. The bowl includes a bowl bottom and a curved bowl wall. The bowl bottom includes a peripheral recessed portion on one side of the bowl bottom. One side of the curved bowl wall is annularly connected to an edge of the side of the bowl bottom, and the other side of the curved bowl wall, which is not connected to the bowl bottom, includes a protruding edge extending toward a central axis of the bowl bottom. The spoon includes a holding portion and a scooping portion connected to the holding portion, and a curve of one end of the scooping portion away from the holding portion matches a curve of the peripheral recessed portion.
    Type: Application
    Filed: August 27, 2020
    Publication date: December 16, 2021
    Inventors: Ming-Hua HUANG, Lung-Hsun SONG, Cheng-Hsin CHEN, Lin-Chun SUN, Jian-Syun LU
  • Publication number: 20210343861
    Abstract: A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.
    Type: Application
    Filed: March 29, 2021
    Publication date: November 4, 2021
    Inventors: Chi-Fu LIN, Cheng-Hsin CHEN, Ming-I HSU, Kun-Ming HUANG, Chien-Li KUO
  • Publication number: 20210279159
    Abstract: A trace configuration calculating method is applied to pivotal connection of a first workpiece and a hinge. A first trace space is formed at a position where the hinge is pivoted to the first workpiece. A first trace is disposed through the first trace space. The trace configuration calculating method includes the hinge and the first workpiece rotating first and second angles to make the first trace space have first and second contour cross-sections respectively, overlapping the first and second contour cross-sections to form a first intersection area, calculating a first maximum inscribed circle according to the first intersection area, and determining a first optimal center and a first maximum diameter of the first trace according to the first maximum inscribed circle.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 9, 2021
    Inventors: Cheng-Hsin Chen, Chun-Hung Lin, Chun-Chieh Chen
  • Publication number: 20210104584
    Abstract: A method of manufacturing a light-emitting panel includes forming a plurality of transistors on a substrate, forming an ILD on the substrate to cover the transistors; and forming a plurality of first through holes penetrating the ILD to partially expose the transistors. The method further includes forming a plurality of conductive features on the ILD and in the first through holes to electrically connect the transistors; forming a first passivation layer on the ILD to cover the conductive features; and planarizing the first passivation layer. The method further includes forming a second through hole penetrating the first passivation layer to partially expose one of the conductive features; and forming a light-emitting device on the planarized first passivation layer, wherein the light-emitting device includes a first electrode formed on the planarized first passivation layer and in the second through hole to electrically connect the exposed conductive feature.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 8, 2021
    Inventors: YUAN-CHING CHANG, CHENG-HSIN CHEN
  • Patent number: 10811636
    Abstract: A light emitting device includes a first type carrier transportation layer and an organic light emitting unit over the first type carrier transportation layer. The light emitting device further includes a second type carrier transportation layer over the organic light emitting unit, wherein the second type is opposite to the first type. At least one of the first type carrier transportation layer and the second type carrier transportation layer includes a metal element.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 20, 2020
    Assignee: INT TECH CO., LTD.
    Inventors: Yu-Hung Chen, Meng-Hung Hsin, Cheng-Hsin Chen
  • Patent number: 10720594
    Abstract: A light emitting device includes a substrate and a light emitting unit over the substrate. The light emitting unit includes a first electrode, an organic emissive layer over the first electrode, a first electron transportation layer over the organic emissive layer, and a metal-containing layer over the first transportation layer. An end of the first electron transportation layer meets the organic emissive layer and the metal-containing layer at a first meeting point, the organic emissive layer has an end which is close to the first meeting point meets the metal-containing layer at a second meeting point, the second meeting point is spaced apart from the first meeting point and away from the first electron transportation layer. Further, at least one of the first electron transportation layer and the metal-containing layer includes transitional metal or alkali metal.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: July 21, 2020
    Assignee: INT TECH CO., LTD.
    Inventors: Cheng-Hsin Chen, Huei-Siou Chen, Li-Chen Wei
  • Publication number: 20200207559
    Abstract: A method for manufacturing a panel and a dust-free system for manufacturing a panel are provided. The method includes several operations. A first operation on a substrate in a first machine station is performed. A second operation on the substrate in a second machine station is performed. The substrate is transferred between the first machine station and the second machine station, wherein the substrate is transferred in a mini-environment by a panel carrier.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Ruei Ken KAO, Cheng-Hsin CHEN
  • Publication number: 20200167389
    Abstract: A searching method includes the following steps: receiving a search keyword, generating a plurality of first graphical nodes, according to the search keyword, recommending a plurality of second graphical nodes, according to the search keyword at least selected one of the plurality of first graphical nodes, and recommending a target graphical node, according to the search keyword at least the selected one of the plurality of first graphical nodes and at least selected one of the plurality of second graphical nodes.
    Type: Application
    Filed: May 23, 2019
    Publication date: May 28, 2020
    Inventors: Cheng-Hsin CHEN, Chun-Hung LIN, Yan-Yue YIN
  • Publication number: 20200167435
    Abstract: A system for synchronous operation display is operated in at least one computer. The system for synchronous operation display includes an input/output (I/O) device, a memory, and a processor. The I/O device is configured to display a screen and receive an operation input. The memory store includes computer code, application programs, and files. The processor is coupled to the I/O device and the memory. The processor is configured to execute the computer program code, in order to provide an object design screen, and display the design specification in the corresponding window.
    Type: Application
    Filed: May 10, 2019
    Publication date: May 28, 2020
    Inventors: Cheng-Hsin CHEN, Chun-Hung LIN
  • Publication number: 20200058715
    Abstract: The present disclosure provides a light emitting device. The light emitting device includes a substrate, an array of light emitting units over the substrate, and an array of bumps. Each of the bumps is disposed between two of the light emitting units. Each of the light emitting units includes a first electrode including a bottom surface on the substrate, a top surface opposite to the bottom surface, and a sidewall between the bottom surface and the top surface. Each of the light emitting units includes a first organic layer on the first electrode and a second organic layer on the first organic layer. The first organic layer at least partially covers the sidewall. A method for manufacturing a light emitting device is also provided.
    Type: Application
    Filed: December 26, 2018
    Publication date: February 20, 2020
    Inventors: FENG YU HUANG, HUEI-SIOU CHEN, CHENG-HSIN CHEN
  • Publication number: 20200058875
    Abstract: The present disclosure provides a method for manufacturing a light emitting device. The method includes providing a substrate, and forming a photosensitive layer over the substrate. The method also includes patterning the photosensitive layer to form a first recess and a first bump. The method also includes disposing a first organic layer in the first recess. The method also includes patterning the photosensitive layer to form a second recess and a second bump. The method also includes disposing a second organic layer in the second recess.
    Type: Application
    Filed: December 26, 2018
    Publication date: February 20, 2020
    Inventors: FENG YU HUANG, HUEI-SIOU CHEN, CHENG-HSIN CHEN