Patents by Inventor Cheng-Hsuan Huang
Cheng-Hsuan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10860774Abstract: The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.Type: GrantFiled: August 9, 2018Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20180349545Abstract: The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.Type: ApplicationFiled: August 9, 2018Publication date: December 6, 2018Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 10049178Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.Type: GrantFiled: June 1, 2016Date of Patent: August 14, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20160275232Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.Type: ApplicationFiled: June 1, 2016Publication date: September 22, 2016Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 9411924Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.Type: GrantFiled: October 11, 2013Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20150106779Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20140061274Abstract: The bicycle carrying bag includes a main bag and a shoulder strap. The main bag is composed of a bag sheet and a soft pad top-dressed on the bag sheet. Edges of the bag sheet are disposed with a first zipper and a second zipper to make the bag sheet form a bag body. Two blanks are remained between the two zippers and are disposed with a pair of Velcro patches. The shoulder strap includes a belt and two belt connectors. Each the belt connector is composed of a first member and a second member. The first member is located at an end of the belt. A loop is formed when the first and second members are engaged for looping up a frame and wheel of a bicycle. The shoulder strap may pass through the pair of Velcro patches.Type: ApplicationFiled: December 10, 2012Publication date: March 6, 2014Inventors: Ting-Wen Huang, Kuo-Yen Huang, Cheng-Hsuan Huang
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Publication number: 20140066241Abstract: A cover for protecting a drivetrain system, which is used when a bicycle is stowed in a carrying bag, is disclosed. The chain bag is a rectangular bag with two hanging belts. The hanging belts are separately disposed with velcro fasteners for hanging on a frame or rack of a bicycle.Type: ApplicationFiled: December 13, 2012Publication date: March 6, 2014Inventors: Ting-Wen Huang, Kuo-Yen Huang, Cheng-Hsuan Huang
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Publication number: 20130284734Abstract: A folding storage device includes a storage box, a vacuum storage bag and a bottom plate. The storage box includes a box body made of soft sheets and frames disposed inside the sides of the box body. The box body can be folded and expanded. The vacuum storage bag has an air valve. After articles are placed into the vacuum storage bag, the vacuum storage bag can be compressed through the air valve and then placed into the storage box. The bottom plate can be twisted and folded and is placed at the bottom of the vacuum storage bag to increase the space of the vacuum bag for the articles to be placed into the bag with ease.Type: ApplicationFiled: April 27, 2012Publication date: October 31, 2013Inventor: Cheng-Hsuan Huang