Patents by Inventor CHENG HUNG WANG

CHENG HUNG WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250208113
    Abstract: The present disclosure provides a material monitoring system for casting concrete. The system includes a monitoring device having a body and an integrated sensor, and the monitoring device is an internet of things (IoT) device. The body of the monitoring device is installed with a power supply and a central processing unit. The integrated sensor is used to measure the real-time temperature and real-time electrical resistance of concrete. Further, the integrated sensor is connected to the bottom surface of the body, and the sensor, the power supply, and the central processing unit are electrically connected. The integrated sensor is immersed in the concrete while the body is situated on the surface of the concrete when the monitoring device is used.
    Type: Application
    Filed: March 7, 2023
    Publication date: June 26, 2025
    Inventors: Takafumi NOGUCHI, Shigeyuki NISHIJIMA, Hiroshi TSUKUI, Kin-Yung CHAN, Cheng-Hung WANG
  • Publication number: 20250180409
    Abstract: A wireless communication device includes: a temperature sensor measuring temperature of concrete within sheathing boards contacting therewith, and transmits signals of the temperature sensor by radio; a flange including a bottom surface flushing with a contact surface of an opening being formed in the sheathing boards; an insertion portion in a tapered conical shape protruding to an inside of a formwork from the flange, and holding the temperature sensor; a head portion with a diameter less than that of the flange exposing to an outside of the formwork from the flange, the wireless communication device is integrated with the concrete whereby: the head portion is fixed by means of a fixing tool until the formwork has not been separated; and the insertion portion is held by hardened and contracted concrete after the formwork has been separated.
    Type: Application
    Filed: March 7, 2023
    Publication date: June 5, 2025
    Inventors: Takafumi NOGUCHI, Shigeyuki NISHIJIMA, Hiroshi TSUKUI, Cheng Hung WANG, Kin Yung CHAN
  • Publication number: 20240371881
    Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.
    Type: Application
    Filed: July 10, 2024
    Publication date: November 7, 2024
    Inventors: Kuan-Jung CHEN, Tsung-Lin LEE, Chung-Ming LIN, Wen-Chih CHIANG, Cheng-Hung WANG
  • Publication number: 20240363495
    Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Kuan-Jung CHEN, Cheng-Hung WANG, Tsung-Lin LEE, Shiuan-Jeng LIN, Chun-Ming LIN, Wen-Chih CHIANG
  • Patent number: 12074169
    Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Jung Chen, Tsung-Lin Lee, Chung-Ming Lin, Wen-Chih Chiang, Cheng-Hung Wang
  • Patent number: 12068227
    Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Jung Chen, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
  • Publication number: 20240222197
    Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.
    Type: Application
    Filed: March 19, 2024
    Publication date: July 4, 2024
    Inventors: Cheng-Hung WANG, Tsung-Lin LEE, Wen-Chih CHIANG, Kuan-Jung CHEN
  • Patent number: 11935795
    Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
  • Patent number: 11894381
    Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Jung Chen, Tsung-Lin Lee, Chung-Ming Lin, Wen-Chih Chiang, Cheng-Hung Wang
  • Publication number: 20230282552
    Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Inventors: Kuan-Jung CHEN, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
  • Patent number: 11688666
    Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Jung Chen, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
  • Patent number: 11508628
    Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
  • Publication number: 20220367276
    Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Cheng-Hung WANG, Tsung-Lin LEE, Wen-Chih CHIANG, Kuan-Jung CHEN
  • Publication number: 20220367523
    Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Kuan-Jung CHEN, Tsung-Lin LEE, Chung-Ming LIN, Wen-Chih CHIANG, Cheng-Hung WANG
  • Publication number: 20220084887
    Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 17, 2022
    Inventors: Cheng-Hung WANG, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
  • Publication number: 20210287963
    Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Inventors: Kuan-Jung Chen, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
  • Patent number: 11031320
    Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Jung Chen, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
  • Publication number: 20200176359
    Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.
    Type: Application
    Filed: November 6, 2019
    Publication date: June 4, 2020
    Inventors: Kuan-Jung Chen, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
  • Publication number: 20200161335
    Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.
    Type: Application
    Filed: October 28, 2019
    Publication date: May 21, 2020
    Inventors: Kuan-Jung CHEN, Tsung-Lin LEE, Chung-Ming LIN, Wen-Chih CHIANG, Cheng-Hung WANG
  • Patent number: 10395997
    Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: August 27, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Cheng Tsao, Cheng-Hung Wang, Chun-Chieh Lin, Hsiu-Hsiung Yang, Yu-Pin Tsai