Abstract: A method of identifying defects in crystals includes the following steps. A silicon carbide crystal to be identified for defects is sliced to obtain a test piece. An etching process is performed on the test piece. Etching conditions of the etching process includes the following. An etchant including potassium hydroxide is used, and etching is performed at a temperature of 400° C. to 550° C. in an environment where dry air or oxygen is introduced, so as to form etching pits of threading edge dislocations (TED) and threading screw dislocations (TSD) in the test piece. After the etching process is performed, a diameter ratio (TED/TSD) of the etching pits of the threading edge dislocations (TED) and the threading screw dislocations (TSD) observed by an optical microscope in the test piece is in a range of 0.2 to 0.5.

Abstract: A wafer processing system and a rework method thereof are provided. An image capture device captures an image of a wafer to generate a captured image. A control device detects a defect pattern in the captured image, calculates a target removal thickness according to distribution of contrast values of the defect pattern, and controls a processing device to perform processing on the wafer according to the target removal thickness.

Abstract: A wafer processing system and a rework method thereof are provided. An image capture device captures an image of a wafer to generate a captured image. A control device detects a defect pattern in the captured image, calculates a target removal thickness according to distribution of contrast values of the defect pattern, and controls a processing device to perform processing on the wafer according to the target removal thickness.

Abstract: A polycrystalline silicon wafer is provided. The polycrystalline silicon wafer, includes a plurality of silicon grains, wherein the carbon content of the polycrystalline silicon wafer is greater than 4 ppma, and the resistivity of the polycrystalline silicon wafer is greater than or equal to 1.55 ?-cm.

Abstract: An N-type polysilicon crystal, a manufacturing method thereof, and an N-type polysilicon wafer are provided. The N-type polysilicon crystal has a slope of resistivity and a slope of defect area percentage. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to resistivity presented by a unit of Ohm·cm (?·cm), the slope of resistivity is 0 to ?1.8 at the solidified fraction of 0.25 to 0.8. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor.

Abstract: A polycrystalline silicon column is provided. The polycrystalline silicon column includes a plurality of silicon grains grown along a crystal-growing direction. In the crystal-growing direction, the average grain size of the silicon grains and the resistivity of the polycrystalline silicon column have opposite variation in their trends, the average grain size of the silicon grains and the oxygen content of the polycrystalline silicon column have opposite variation in their trends, and the average grain size of the silicon grains and the defect area ratio of the polycrystalline silicon column have the same variation in their trends. The overall average defect area ratio of the polycrystalline silicon column is less than or equal to 2.5%.

Abstract: An N-type polysilicon crystal, a manufacturing method thereof, and an N-type polysilicon wafer are provided. The N-type polysilicon crystal has a slope of resistivity and a slope of defect area percentage. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to resistivity presented by a unit of Ohm·cm (?·cm), the slope of resistivity is 0 to ?1.8 at the solidified fraction of 0.25 to 0.8. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device includes a substrate; two fins located on the substrate and extending along a first direction; an isolation material layer surrounding the fins, comprising a first isolation regions located at an end region between the two fins along the first direction, and a second isolation region located at sides of the fins along a second direction that is different from the first direction, wherein an upper surface of the first isolation region substantially align with an upper surfaces of the fins, and an upper surface of the second isolation region is lower than the upper surface of the fins; and a first insulating layer on the first isolation region.

Abstract: A solar cell wafer is provided. It is a silicon wafer, and a surface of the silicon wafer has a plurality of pores, wherein based on a total amount of 100% of the plurality of pores, 60% or more of the pores has a circularity greater than 0.5. Therefore, the reflectance of the solar cell wafer can be efficiently reduced.

Abstract: A crystalline silicon ingot and a method of fabricating the same are disclosed. The crystalline silicon ingot of the invention includes multiple silicon crystal grains growing in a vertical direction of the crystalline silicon ingot. The crystalline silicon ingot has a bottom with a silicon crystal grain having a first average crystal grain size of less than about 12 mm. The crystalline silicon ingot has an upper portion, which is about 250 mm away from said bottom, with a silicon crystal grain having a second average crystal grain size of greater than about 14 mm.

Abstract: The present disclosure provides a polycrystalline silicon ingot. The polycrystalline silicon ingot has a vertical direction and includes a nucleation promotion layer located at a bottom of the polycrystalline silicon ingot, and silicon grains grown along the vertical direction, wherein the silicon grains include at least three crystal directions. The coefficient of variation of grain area in a section above the nucleation promotion layer of the polycrystalline silicon ingot increases along the vertical direction.

Abstract: A method of fabricating a poly-crystalline silicon ingot includes: (a) loading a nucleation promotion layer onto a bottom of a mold; (b) providing a silicon source on the nucleation promotion layer in the mold; (c) heating the mold until the silicon source is melted into a silicon melt completely; (d) controlling at least one thermal control parameter regarding the silicon melt continually to enable the silicon melt to nucleate on the nucleation promotion layer such that a plurality of silicon grains grow in the vertical direction; (e) controlling the at least one thermal control parameter to enable the plurality of the silicon grains to continuously grow with an average grain size increasing progressively in the vertical direction until entirety of the silicon melt is solidified to obtain the poly-crystalline silicon ingot, wherein the nucleation promotion layer is loaded by spreading a plurality of mono-Si particles over the bottom of the mold.

Abstract: A poly-crystalline silicon ingot having a bottom and defining a vertical direction includes a plurality of silicon grains grown in the vertical direction, in which the plurality of the silicon grains have at least three crystal orientations; and a nucleation promotion layer comprising a plurality of chips and chunks of poly-crystalline silicon on the bottom, wherein the poly-crystalline silicon ingot has a defect density at a height ranging from about 150 mm to about 250 mm of the poly-crystalline silicon ingot that is less than 15%.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor.

Abstract: A poly-crystalline silicon ingot having a bottom and defining a vertical direction includes a plurality of silicon grains grown in the vertical direction, in which the plurality of the silicon grains have at least three crystal orientations; and a nucleation promotion layer comprising a plurality of chips and chunks of poly-crystalline silicon on the bottom, wherein the poly-crystalline silicon ingot has a defect density at a height ranging from about 150 mm to about 250 mm of the poly-crystalline silicon ingot that is less than 15%.

Abstract: A crystalline silicon ingot and a method of fabricating the same are provided. The method utilizes a nucleation promotion layer to facilitate a plurality of silicon grains to nucleate on the nucleation promotion layer from a silicon melt and grow in a vertical direction into silicon grains until the silicon melt is completely solidified. The increment rate of defect density in the silicon ingot along the vertical direction has a range of 0.01%/mm˜10%/mm.

Abstract: A method of fabricating a poly-crystalline silicon ingot includes: (a) loading a nucleation promotion layer onto a bottom of a mold; (b) providing a silicon source on the nucleation promotion layer in the mold; (c) heating the mold until the silicon source is melted into a silicon melt completely; (d) controlling at least one thermal control parameter regarding the silicon melt continually to enable the silicon melt to nucleate on the nucleation promotion layer such that a plurality of silicon grains grow in the vertical direction; (e) controlling the at least one thermal control parameter to enable the plurality of the silicon grains to continuously grow with an average grain size increasing progressively in the vertical direction until entirety of the silicon melt is solidified to obtain the poly-crystalline silicon ingot, wherein the nucleation promotion layer is loaded by spreading a plurality of mono-Si particles over the bottom of the mold.

Abstract: A polycrystalline silicon column is provided. The polycrystalline silicon column includes a plurality of silicon grains grown along a crystal-growing direction. In the crystal-growing direction, the average grain size of the silicon grains and the resistivity of the polycrystalline silicon column have opposite variation in their trends, the average grain size of the silicon grains and the oxygen content of the polycrystalline silicon column have opposite variation in their trends, and the average grain size of the silicon grains and the defect area ratio of the polycrystalline silicon column have the same variation in their trends. The overall average defect area ratio of the polycrystalline silicon column is less than or equal to 2.5%.

Abstract: A polycrystalline silicon wafer is provided. The polycrystalline silicon wafer, includes a plurality of silicon grains, wherein the carbon content of the polycrystalline silicon wafer is greater than 4 ppma, and the resistivity of the polycrystalline silicon wafer is greater than or equal to 1.55 ?-cm.