Abstract: The present disclosure provides a polycrystalline silicon ingot, a polycrystalline silicon brick and a polycrystalline silicon wafer. The polycrystalline silicon ingot has a vertical direction and includes a nucleation promotion layer located at a bottom of the polycrystalline silicon ingot, and a plurality of silicon grains grown along the vertical direction, wherein the silicon grains include at least three crystal directions. The coefficient of variation of grain area in a section above the nucleation promotion layer of the polycrystalline silicon ingot increases along the vertical direction.

Abstract: A crystalline silicon ingot and a method of fabricating the same are provided. The method utilizes a nucleation promotion layer to facilitate a plurality of silicon grains to nucleate on the nucleation promotion layer from a silicon melt and grow in a vertical direction into silicon grains until the silicon melt is completely solidified. The increment rate of defect density in the silicon ingot along the vertical direction has a range of 0.01%/mm˜10%/mm.

Abstract: A crystalline silicon ingot and a method of fabricating the same are disclosed. The crystalline silicon ingot of the invention includes multiple silicon crystal grains growing in a vertical direction of the crystalline silicon ingot. The crystalline silicon ingot has a bottom with a silicon crystal grain having a first average crystal grain size of less than about 12 mm. The crystalline silicon ingot has an upper portion, which is about 250 mm away from said bottom, with a silicon crystal grain having a second average crystal grain size of greater than about 14 mm.

Abstract: A crystalline silicon ingot and a method of fabricating the same are disclosed. The crystalline silicon ingot of the invention includes multiple silicon crystal grains growing in a vertical direction of the crystalline silicon ingot. The crystalline silicon ingot has a bottom with a silicon crystal grain having a first average crystal grain size of less than about 12 mm. The crystalline silicon ingot has an upper portion, which is about 250 mm away from said bottom, with a silicon crystal grain having a second average crystal grain size of greater than about 14 mm.

Abstract: A crystalline silicon ingot and a method of fabricating the same are provided. The method utilizes a nucleation promotion layer to facilitate a plurality of silicon grains to nucleate on the nucleation promotion layer from a silicon melt and grow in a vertical direction into silicon grains until the silicon melt is completely solidified. The increment rate of defect density in the silicon ingot along the vertical direction has a range of 0.01%/mm˜10%/mm.

Abstract: A crystalline silicon ingot and a method of fabricating the same are provided. The method utilizes a nucleation promotion layer to facilitate a plurality of silicon grains to nucleate on the nucleation promotion layer from a silicon melt and grow in a vertical direction into silicon grains until the silicon melt is completely solidified. The increment rate of defect density in the silicon ingot along the vertical direction has a range of 0.01%/mm˜10%/mm.

Abstract: A crystalline silicon ingot and a method of fabricating the same are disclosed. The crystalline silicon ingot of the invention includes multiple silicon crystal grains growing in a vertical direction of the crystalline silicon ingot. The crystalline silicon ingot has a bottom with a silicon crystal grain having a first average crystal grain size of less than about 12 mm. The crystalline silicon ingot has an upper portion, which is about 250 mm away from said bottom, with a silicon crystal grain having a second average crystal grain size of greater than about 14 mm.

Abstract: A method to etch passivation layers and an antireflective layer on a substrate, comprising: forming a metal layer on the substrate; forming the antireflective layer on the metal layer; forming the passivation layers on the antireflective layer, wherein the passivation layer consisting of a silicon oxide layer on the antireflective layer and a silicon nitride layer on the silicon oxide layer; etching the silicon nitride layer in a first etching chamber, wherein the silicon nitride layer is etched in a uniformity of less than 10% in the first etching chamber; etching the silicon oxide layer in a second etching chamber, wherein the silicon oxide layer is etching in a uniformity of less than 5% in the second etching chamber; etching the antireflective layer in the second etching chamber to expose a surface of the metal layer for metal contacts of integrated circuits.