Patents by Inventor Cheng Kuo

Cheng Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240025406
    Abstract: A method for adjusting speed of instant vehicle is provided. The method obtains a preset speed of the instant vehicle and a real position of the instant vehicle. The method determines a corresponding detection distance according to the preset speed of the instant vehicle. The method obtains a road congestion status within a range of the corresponding detection distance according to the real position of the instant vehicle. The method adjusts the preset speed of the instant vehicle according to the road congestion status within the range of the corresponding detection distance. A related electronic device and a non-transitory storage medium are provided.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 25, 2024
    Inventor: CHENG-KUO YANG
  • Patent number: 11862512
    Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
  • Patent number: 11855025
    Abstract: A semiconductor device includes a conductive pad having a first width. The semiconductor device includes a passivation layer over the conductive pad, wherein the passivation layer directly contacts the conductive pad. The semiconductor device includes a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The semiconductor device includes an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device includes a conductive pillar on the UBM layer.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chita Chuang, Yao-Chun Chuang, Tsung-Shu Lin, Chen-Cheng Kuo, Chen-Shien Chen
  • Publication number: 20230394306
    Abstract: Provided is an efficient multi-modal processing model. The multi-modal processing model can process input data from multiple different domains to generate a prediction for a multi-modal processing task. A machine-learned multi-modal processing model can include an adaptive tokenization layer that is configured to adaptively tokenize features generated from the multi-modal inputs into sets of tokens. Specifically, the tokens may have a smaller data size relative to the features from the inputs, thereby enabling a reduced number of processing operations to be performed overall, thereby improving the efficiency of model.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 7, 2023
    Inventors: Anthony J. Piergiovanni, Wei-Cheng Kuo, Anelia Angelova
  • Publication number: 20230382716
    Abstract: Various embodiments of the present disclosure are directed towards an electronic device that comprises a semiconductor substrate having a first surface opposite a second surface. The semiconductor substrate at least partially defines a cavity. A first microelectromechanical systems (MEMS) device is disposed along the first surface of the semiconductor substrate. The first MEMS device comprises a first backplate and a diaphragm vertically separated from the first backplate. A second MEMS device is disposed along the first surface of the semiconductor substrate. The second MEMS device comprises spring structures and a moveable element. The spring structures are configured to suspend the moveable element in the cavity. A segment of the semiconductor substrate continuously laterally extends from under a sidewall of the first MEMS device to under a sidewall of the second MEMS device.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Chun Yin Tsai, Wen Cheng Kuo
  • Publication number: 20230371732
    Abstract: A container assembly in accordance with one embodiment of the present disclosure includes an outer container having a first open end and a second closed end and defining an inner cavity; and a plunging assembly configured to be received within the outer container, the plunging assembly having a first end and a second end, wherein the plunging assembly includes an inner sleeve having a first end and a second end and a wall defining an inner bore, and wherein the plunging assembly includes an extraction assembly having a body having a first end and a second end and a side wall extending for at least a portion of the distance between the first and second ends of the body, wherein the first end of the body is coupled to the inner sleeve at or near the second end of the inner sleeve, and wherein the body includes a first sieve portion, and wherein the extraction assembly further includes a strainer having a second sieve portion, wherein the strainer is removably couplable to the body.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 23, 2023
    Inventors: Travis Merrigan, Patrick Crosby, Scott Rolfson, Cheng Kuo Lin, Kai Chuan Chuang
  • Publication number: 20230377951
    Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
  • Patent number: 11807521
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a microelectromechanical systems (MEMS) device. The method includes forming a filter stack over a carrier substrate. The filter stack comprises a particle filter layer having a particle filter. A support structure layer is formed over the filter stack. The support structure layer is patterned to define a support structure in the support structure layer such that the support structure has one or more segments. The support structure is bonded to a MEMS structure.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Wen Cheng Kuo
  • Patent number: 11806710
    Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: November 7, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiao-Yen Lee, Ying-Te Ou, Chin-Cheng Kuo, Chung Hao Chen
  • Patent number: 11784110
    Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 10, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung Hao Chen, Chin-Cheng Kuo
  • Patent number: 11784111
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: October 10, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Chin-Cheng Kuo, Wu Chou Hsu
  • Publication number: 20230307251
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 28, 2023
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 11756929
    Abstract: A semiconductor package includes a first chip, a first chip and a molding compound. The first chip has a first via protruding from the first chip. The second chip has a second via protruding from the second chip, wherein a thickness of the first chip is different from a thickness of the second chip. The molding compound encapsulates the first chip, the second chip, the first via and the second via, wherein surfaces of the first via, the second via and the molding compound are substantially coplanar.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
  • Patent number: 11740283
    Abstract: The present invention relates to a multistory electronic device testing apparatus, which mainly comprises a feeding and binning device, a multi-axis transfer device, a chip-testing device and a main controller. The feeding and binning device includes an upper module and a lower module. The chip-testing device includes a plurality of testing units arranged vertically. The main controller not only controls the feeding, binning and testing operations, but also controls the multi-axis transfer device to transfer an electronic device to be tested or a tested electronic device between the feeding and binning device and the chip-testing device. Accordingly, the three-dimensional arrangement of the feeding and binning module and the testing device is realized, and the accommodating capacity and the testing capacity for the electronic devices to be tested and the tested electronic devices can be increased.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: August 29, 2023
    Assignee: CHROMA ATE INC.
    Inventors: Chin-Yi Ouyang, Chien-Ming Chen, Wei-Cheng Kuo, Xin-Yi Wu, Iching Tsai
  • Patent number: 11708402
    Abstract: This invention reveals the potential applications of modified porcine plasma fibronectin that could be applied as a safe material for clinical wound healing and tissue repair. In order to seek safe sources of plasma fibronectin for practical consideration in wound dressing, this invention isolated and modified fibronectin from porcine plasma and demonstrated that modified porcine plasma fibronectin has similar ability as homo plasma fibronectin being as a suitable substrate for stimulation of cell adhesion and directed cell migration. The present invention also reveals a material and a pharmaceutical composition enhance wound healing.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: July 25, 2023
    Assignee: National Yang Ming Chiao Tung University
    Inventor: Jean-Cheng Kuo
  • Patent number: 11699598
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: July 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20230173920
    Abstract: A method of automatically switching between manners of answering calls by vehicle occupants in a vehicle connects a vehicle-mounted system with terminal device of occupant. Information as to persons in the vehicle is detected. Information as to different occupants allows method to recommend one of a first manner, a second manner, and a third manner of responding to an incoming call, the driver being able to select his preferred manner by pushbutton mounted on steering wheel. Driving safety is improved, and privacy of a personal conversation can be maintained. A vehicle-mounted system applying the method is also disclosed.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 8, 2023
    Inventors: CHENG-KUO YANG, SHAO-YANG LIU
  • Patent number: 11660494
    Abstract: A push-up exercise device with height adjustment includes two bases and a grab rail mounted to and located between the two bases. Each base is provided with a mounting hole at a center of the base and a positioning piece in the mounting hole. A plurality of mounting slots with different lengths are disposed inside a mounting rod of the grab rail, extending from an open end of the mounting rod and corresponding to the positioning piece. The positioning pieces are configured to be aligned with and mounted into different lengths of the mounting slots to adjust a height of the grab rail of the push-up exercise device and in order to train different muscle groups and further shape a body of a user and improve the fitness of the user.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: May 30, 2023
    Assignee: Shanq Dih Co., Ltd.
    Inventor: Cheng-Kuo Cheng
  • Patent number: 11649162
    Abstract: Various embodiments of the present disclosure are directed towards a method for manufacturing a microelectromechanical systems (MEMS) device. The method includes forming a particle filter layer over a carrier substrate. The particle filter layer is patterned while the particle filter layer is disposed on the carrier substrate to define a particle filter in the particle filter layer. A MEMS substrate is bonded to the carrier substrate. A MEMS structure is formed over the MEMS substrate.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng, Wen Cheng Kuo
  • Patent number: 11631631
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, a conductive structure and at least one via structure. The conductive structure is disposed on an upper surface of the semiconductor substrate. The at least one via structure is disposed in the semiconductor substrate. A portion of the at least one via structure extends beyond the conductive structure.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: April 18, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chin-Cheng Kuo