Abstract: A bit line is pre-charged based on a clock signal internal to a bit line pre-charge circuit when a bit line pre-charge window is within a margin of a predetermined pre-charge window. A bit line is pre-charged based on a clock signal external to the bit line pre-charge circuit when the bit line pre-charge window is outside the margin of the predetermined pre-charge window.

Abstract: A bit line is pre-charged based on a clock signal internal to a bit line pre-charge circuit when a bit line pre-charge window is within a margin of a predetermined pre-charge window. A bit line is pre-charged based on a clock signal external to the bit line pre-charge circuit when the bit line pre-charge window is outside the margin of the predetermined pre-charge window.

Abstract: An integrated circuit (IC) package includes a one or more die and an interposer. The interposer is coupled to the die and includes circuit traces. The circuit traces are provided in a serpentine configuration. A method can be used to fabricate an integrated circuit package.

Abstract: An integrated circuit (IC) package includes a one or more die and an interposer. The interposer is coupled to the die and includes circuit traces. The circuit traces are provided in a serpentine configuration. A method can be used to fabricate an integrated circuit package. The method can use an interposer circuit traces having a configuration that allows the circuit traces to deform under stress, and return to an original state undamaged more readily than a straight conductive trace.

Abstract: Memory devices are disclosed that support multiple power ramping sequences or modes. For example, a level shifter device is operably connected to a memory macro in a memory device. The level shifter device receives at least one gating signal. Based on a state of the at least one gating signal, the level shifter device outputs one or more signals that cause or control voltage signals in or received by the memory macro to ramp up, ramp down, or ramp up and ramp down according to one or more power ramping modes.

Abstract: An integrated circuit (IC) package includes a one or more die and an interposer. The interposer is coupled to the die and includes circuit traces. The circuit traces are provided in a serpentine configuration. A method can be used to fabricate an integrated circuit package.

Abstract: A bit line is pre-charged based on a clock signal internal to a bit line pre-charge circuit when a bit line pre-charge window is within a margin of a predetermined pre-charge window. A bit line is pre-charged based on a clock signal external to the bit line pre-charge circuit when the bit line pre-charge window is outside the margin of the predetermined pre-charge window.

Abstract: A bit line is pre-charged based on a clock signal internal to a bit line pre-charge circuit when a bit line pre-charge window is within a margin of a predetermined pre-charge window. A bit line is pre-charged based on a clock signal external to the bit line pre-charge circuit when the bit line pre-charge window is outside the margin of the predetermined pre-charge window.

Abstract: Memory devices are disclosed that support multiple power ramping sequences or modes. For example, a level shifter device is operably connected to a memory macro in a memory device. The level shifter device receives at least one gating signal. Based on a state of the at least one gating signal, the level shifter device outputs one or more signals that cause or control voltage signals in or received by the memory macro to ramp up, ramp down, or ramp up and ramp down according to one or more power ramping modes.

Abstract: A vital signs measurement system includes a plurality of light sources emitting into a subject's skin. A plurality of photo sensors receives lights reflected from the subject's skin and converts the lights to a plurality of signals. A processing module receives the plurality of signals and transforms the plurality of signals to a PPG signal by analyzing a correlation coefficient between every two ones of the plurality of signals. The vital signs measurement system improves the measurement accuracy of the physiological information of the participant by the correlation coefficient.

Abstract: A vital signs measurement system includes a plurality of light sources emitting into a subject's skin. A plurality of photo sensors receives lights reflected from the subject's skin and converts the lights to a plurality of signals. A processing module receives the plurality of signals and transforms the plurality of signals to a PPG signal by analyzing a correlation coefficient between every two ones of the plurality of signals. The vital signs measurement system improves the measurement accuracy of the physiological information of the participant by the correlation coefficient.

Abstract: A heart rate detection earphone is worn on an auricle which has a cavitas conchae. The heart rate detection earphone includes an earphone body matched with and buckled in the auricle, a light guiding module disposed to the earphone body, and an optical sensor. The light guiding module defines a sensing surface exposed out of the earphone body, and the sensing surface abuts against the cavitas conchae. The optical sensor includes a light emitter and a light receiver respectively coupled with the light guiding module. Light beams emitted by the light emitter are guided by the light guiding module to irradiate the cavitas conchae. The light beams emitted by the light emitter are reflected by the cavitas conchae, and then the reflected light beams reflected by the cavitas conchae are returned to and are received by the light receiver through the light guiding module.

Abstract: A smart watch with an ultraviolet (UV) detector includes a base body, a display module, a UV detector module and a processor module. The base body includes a top housing and a watchband. The top housing defines a receiving chamber. At least one lateral face of the top housing is an inclined face. The inclined face is recessed inward and slantwise downward to form a groove. The display module is disposed in the receiving chamber. The UV detector module is disposed in the groove and exposed outward through the groove, wherein in use, the UV detector module is located outward and upward back to a user's body for gaining UV information. The processor module is disposed in the receiving chamber and electrically connected to the display module and the UV detector module. The processor module processes the UV information and then displays processed results on the display module.

Abstract: The present invention discloses a memory device. In one embodiment of the present invention, the memory device includes at least one memory array having a plurality of memory cells addressed by a plurality of word lines and bit lines. At least one word line decoder is coupled to the word lines for selecting the memory cell for read or write operation. The word line decoder includes at least one last stage driver having at least one PMOS transistor and at least one NMOS transistor, the PMOS transistor having a threshold voltage substantially higher than that of the NMOS transistor, thereby reducing the power consumption of the memory device in the stand-by mode.

Abstract: A word-line driver has an input from a word-line decoder and an output to drive a word-line. The word-line driver comprises a plurality of inverters connected in series between the input and output including a first and a second inverter with a first node designating an output of the first inverter and an input of the second inverter, the first inverter having a NMOS transistor with a controllable first source, and a first pull-up circuitry coupled between a positive supply voltage and the first node and selectively activated by a first control signal, wherein when the first source is set to the positive supply voltage and the first control signal is set to a complementary supply voltage of the positive supply voltage, the first node is pulled up to the positive supply voltage to ensure an output of the second inverter is pulled down to the complementary supply voltage.

Abstract: The present invention relates to the discovery the 5?-AMP and analogues thereof can be used to induce a state of torpor or suspended animation in subjects, as exemplified by studies carried out in laboratory mice. In these studies, mice were injected with high doses of 5?-AMP, which was found to result in a decoupling of the animals' body temperature regulation mechanism accompanied by a reduction in the animals' core body temperature, which tended to lower towards the ambient environmental temperature. It was further discovered that the introduction of high levels of 5?-AMP resulted in an induction of fat regulation genes such as procolipase (Clps) in tissues and organs that do not normally express Clps, this in turn was accompanied by a shift in metabolism from a primarily glycolytic energy metabolism (which is inhibited at lower temperatures) to one that relied primarily on the liberation and metabolism of free fatty acids.

Abstract: The present invention is a device for mounting to a bathroom wall and supporting a person's foot during shaving. The device comprises a suction member engageable with the wall to form a suction cavity. The device further comprises a support housing engageable with the suction member and having a central hole. The device further comprises a screw member engaged with the suction member and extending thru the central hole of the support housing. The device further comprises a fastener member engageable with the screw member to increase the volume of said suction cavity thereby creating a vacuum to secure said suction member to the wall. The device further comprises a platform extending outward from the support housing for supporting the person's foot.

Abstract: A projection system comprises a light source module and a light-guiding assembly. The light source module comprises a reflecting cover and a light source disposed in the reflecting cover to form a first beam with a first f-number. The light-guiding assembly comprises a body with an incident end and a lens disposed on the incident end. The first beam passes through the lens disposed on the incident end to form a second beam with a second f-number. The second f-number of the second beam is different from the first f-number of the first beam.

Abstract: A memory device includes a memory array, an I/O circuit for accessing the memory array, and a tracking circuit. The tracking circuit includes a dummy bit line, a first tracking cell including a first NMOS transistor, the first tracking cell being coupled to receive a control signal and also coupled to the dummy bit line through the first NMOS transistor, and a second tracking cell including a second NMOS transistor, the second tracking cell being coupled to receive the control signal and also coupled to the dummy bit line through the second NMOS transistor, a gate of the second NMOS transistor being coupled to the dummy bit line. The memory device also includes a control circuit coupled to the dummy bit line for generating a clock signal for the I/O circuit.