Patents by Inventor Cheng Lee

Cheng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240124844
    Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 18, 2024
    Inventors: Chia-Hsin Lee, Po-Cheng Lin, Yong-Cheng Kao, Ming-Hsi Chuang, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Patent number: 11963293
    Abstract: A method for manufacturing a circuit board structure with a waveguide is provided. The method includes: providing a first substrate unit, a second substrate unit, a third substrate unit, and two adhesive layers, the first substrate unit including a first dielectric layer and a first conductive layer, the first conductive layer including a first shielding area and two first artificial magnetic conductor areas disposed on two sides of the first shielding area; the second substrate unit including a second dielectric layer and a second conductive layer, the second conductive layer including a second shielding area; the third substrate unit defining a first slot, and the adhesive layer defining a second slot; stacking the first substrate unit, one of the adhesive layers, the third substrate unit, another one of the adhesive layers, and the second substrate unit in that order; pressing the intermediate body.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 16, 2024
    Assignee: BOARDTEK ELECTRONICS CORPORATION
    Inventor: Chien-Cheng Lee
  • Patent number: 11961777
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11960201
    Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Cheng Hsu, Chun-Fu Yang, Ta-Cheng Lien, Hsin-Chang Lee
  • Publication number: 20240117314
    Abstract: The present invention relates to a method for preparing a modified stem cell, including the following steps: a cell culture step: culturing stem cells in a first culture medium of a culture dish at a predetermined cell density, and removing the first culture medium after a first culture time to obtain a first cell intermediate; an activity stimulation step: preserving the first cell intermediate in a freezing container having a cell cryopreservation solution, and performing a constant temperature stimulation treatment or a variable temperature stimulation treatment for at least more than 1 day; and a product collection step: after completing the activity stimulation step, placing the freezing container in an environment at a thawing temperature for thawing, and then removing the cell cryopreservation solution to obtain the modified stem cell. The modified stem cell can release at least one or more of IL-4, IL-5, IL-13, G-CSF, Fractalkine, and EGF.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 11, 2024
    Inventors: Ruei-Yue Liang, Chia-Hsin Lee, Kai-Ling Zhang, Po-Cheng Lin, Ming-Hsi Chuang, Yu-Chen Tsai, Peggy Leh Jiunn Wong
  • Publication number: 20240115616
    Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Publication number: 20240116356
    Abstract: A vehicle water-cooling heat sink plate having fin sets with different fin pitch distances is provided. The vehicle water-cooling heat sink plate includes a heat-dissipating plate body and three fin sets. The heat-dissipating plate body has a first heat-dissipating surface and a second heat-dissipating surface that are opposite to each other, the first heat-dissipating surface is used for contacting three traction inverter power component sets, and the second heat-dissipating surface is used for contacting a cooling fluid. The second heat-dissipating surface of the heat-dissipating plate body along a flow direction of the cooling fluid is divided into three heat-dissipating areas which are spaced apart from each other and have the same size, and the three heat-dissipating areas respectively correspond to three projection areas that are respectively generated by the three traction inverter power component sets.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: KUO-WEI LEE, CHUN-LI HSIUNG, CHIEN-CHENG WU, CHUN-LUNG WU
  • Publication number: 20240120288
    Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes a substrate, an encapsulant and an electronic component. The encapsulant is disposed over the substrate, and has a first top surface, a second top surface and a first lateral surface extending between the first top surface and the second top surface. A roughness of the first lateral surface is less than or equal to a roughness of the second top surface. The electronic component is disposed over the second top surface of the encapsulant and electrically connected to the substrate.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 11, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Hsin LAI, Chih-Cheng LEE, Shao-Lun YANG, Wei-Chih CHO
  • Publication number: 20240120812
    Abstract: An integrated motor and drive assembly is disclosed and includes a housing, a motor and a drive. The housing includes a motor-accommodation portion and a drive-accommodation portion. The drive includes a power board and a control board. The power board is made of a high thermal conductivity substrate and includes a power element and an encoder disposed on the first side, the first side faces the motor, the power board and the motor are stacked along a first direction, and the second side contacts the housing to from a heat-dissipating route. The control board is disposed adjacent to the power board. The control board and the power board are arranged along a second direction perpendicular to the first direction, and the first direction is parallel to an axial direction of the motor. A part of the power board and a part of the control board are directly contacted to form an electrical connection.
    Type: Application
    Filed: July 17, 2023
    Publication date: April 11, 2024
    Inventors: Chi-Hsiang Kuo, Yi-Yu Lee, Zuo-Ying Wei, Yuan-Kai Liao, Wen-Cheng Hsieh
  • Publication number: 20240120236
    Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 11, 2024
    Inventors: Tai-Jung Kuo, Po-Cheng Shih, Wan Chen Hsieh, Zhen-Cheng Wu, Chia-Hui Lin, Tze-Liang Lee
  • Publication number: 20240121913
    Abstract: A vehicle water-cooling heat sink plate having fin sets with different surface areas is provided. The vehicle water-cooling heat sink plate includes a heat-dissipating plate body and three fin sets. The heat-dissipating plate body has a first heat-dissipating surface and a second heat-dissipating surface that are opposite to each other, the first heat-dissipating surface is used for contacting three traction inverter power component sets, and the second heat-dissipating surface is used for contacting a cooling fluid. The second heat-dissipating surface of the heat-dissipating plate body along a flow direction of the cooling fluid is divided into three heat-dissipating areas which are spaced apart from each other and have the same size, and the three heat-dissipating areas respectively correspond to three projection areas that are respectively generated by the three traction inverter power component sets.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: CHUN-LI HSIUNG, KUO-WEI LEE, CHUN-LUNG WU, CHIEN-CHENG WU
  • Patent number: 11955173
    Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Elia Ambrosi, Cheng-Hsien Wu, Hengyuan Lee, Chien-Min Lee, Xinyu Bao
  • Patent number: 11955718
    Abstract: The present invention discloses a waterproof microphone kit adapted to be fixed in an electronic device. The waterproof microphone kit includes a housing, a waterproof breathable film, a plug, a circuit motherboard, a microphone unit and a flexible electrical connection component. Two adjacent sides of the housing are provided with an opening and a lateral opening. The waterproof breathable film is disposed at the housing and seals the lateral opening. The plug plugs the opening. The plug, the waterproof breathable film and the housing jointly form an enclosed space. The circuit motherboard is disposed in the housing. The microphone unit is disposed at the circuit motherboard, and a sound receiving part thereof faces the waterproof breathable film. The flexible electrical connection component is connected to the circuit motherboard, and passes through a through hole of the plug so as to connect to an external processing module.
    Type: Grant
    Filed: August 14, 2021
    Date of Patent: April 9, 2024
    Assignee: GETAC HOLDINGS CORPORATION
    Inventor: Kun-Cheng Lee
  • Patent number: 11957064
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Patent number: 11955439
    Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
  • Patent number: 11955191
    Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Perng-Fei Yuh, Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee, Yih Wang
  • Patent number: 11949002
    Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Hsieh Wong, Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20240105750
    Abstract: A CMOS image sensor includes PDAF pixels distributed in an array of image pixels in plan view. Each PDAF pixel includes m×m binned photodiodes, a PDAF color filter overlying the binned photodiodes and laterally surrounded by a first isolation structure, and a PDAF micro-lens overlying the PDAF color filter. A first horizontal distance between a center of the PDAF color filter and a center of the binned photodiodes varies depending on a location of the PDAF pixel in plan view in the CMOS image sensor. Additionally, the first isolation structure includes a first low-n dielectric grid, a second low-n dielectric grid underlying the first low-n dielectric grid, and a metal grid enclosed by the second low-n dielectric grid. The second low-n dielectric grid includes a filler dielectric material different from a second low-n dielectric grid material. Thus, quantum efficiency and uniformity of the CMOS image sensor are improved.
    Type: Application
    Filed: February 16, 2023
    Publication date: March 28, 2024
    Inventors: Ming-Hsien YANG, Chun-Hao Chou, Kuo-Cheng Lee
  • Publication number: 20240103358
    Abstract: A system includes a mask. The system further includes a pellicle frame attached to the mask. The pellicle frame includes a check valve, wherein the check valve is configured to permit gas flow from a first side of the pellicle from to a second side of the pellicle frame. The pellicle frame further includes a flat bottom surface having only a single recess therein, wherein the flat bottom surface is free of an adhesive. The system further includes a gasket within the single recess.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Inventors: Chue San YOO, Hsin-Chang LEE, Pei-Cheng HSU, Yun-Yue LIN