Abstract: A system and network devices for packet processing, a network device including a processor and instructions for receiving a first packet sent by a second network node, the first packet including a format of a segment identifier of the second network node describing a length and a location of each field in the segment identifier, obtaining the format based on the first packet, the segment identifier having a first field, and including a determined value of the first field in the segment identifier in a second packet sent to the second network node, the value of the first field in the segment identifier being determined based on a segment routing policy and the format, and the determined value of the first field indicating to the second network node to process the second packet.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: A battery cell, a battery module, a battery pack, and an electrical apparatus are provided. The battery cell includes an intermediate portion and side portions located on two sides of the intermediate portion in a thickness direction, the intermediate portion comprising m battery cell sub-units and the side portions comprising n battery cell sub-units, where m+n is an integer greater than or equal to 3. Each of the battery cell sub-units comprises a positive electrode sheet, a negative electrode sheet and a separator arranged between the positive electrode sheet and the negative electrode sheet, and each of the m battery cell sub-units has a dry battery cell nail penetration short-circuit resistance greater than that of each of the n battery cell sub-units.

Abstract: This application provides a trace chain information query method, including: receiving, by a trace chain server, first trace chain information sent by a first service node and second trace chain information sent by a second service node, where the first service node is a service node in a first trace chain, the second service node is a service node in a second trace chain, both the first trace chain and the second trace chain are generated as triggered by a same user operation, the first trace chain information includes a group identifier, the second trace chain information includes the group identifier, and the group identifier is used to indicate the user operation; and finding, by the trace chain server, the first trace chain information and the second trace chain information based on the group identifier.

Abstract: This application provides a positioning information transmission method and apparatus, and relates to the field of wireless communication technologies. In the method, a terminal device may receive first information from a network device. The first information may be used to request capability information of the terminal device. The terminal device may send first capability information to the network device. The first capability information may include capability information of sending a reference signal by the terminal device based on a first bandwidth. The first bandwidth herein is greater than a second bandwidth, the first bandwidth may be used by the terminal device to send the reference signal, and the second bandwidth may be used by the terminal device to receive and/or send communication data.

Abstract: A positive electrode current collector and a positive electrode plate, a battery, a battery module, a battery pack, and an apparatus including the positive electrode current collector are provided. In some embodiments, a positive electrode current collector is provided, including an organic support layer and an aluminum-based conductive layer disposed on at least one surface of the organic support layer, where the aluminum-based conductive layer contains Al and at least one modifying element selected from O, N, F, B, S, and P, an XPS spectrogram of the aluminum-based conductive layer with a surface passivation layer removed through etching has at least a first peak falling in a range of 70 eV to 73.5 eV and a second peak falling in a range of 73.5 eV to 78 eV, and a ratio x of peak intensity of the second peak to that of the first peak satisfies 0<x?3.0.

Abstract: The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels.

Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

Abstract: An obstacle avoidance method for a robot arm is provided, including a modeling step, a collecting and evaluating coordinates step, an obtaining control parameter step, an establishing an occupation function step, and a finding an obstacle avoiding posture step. The present invention pre-stores the data obtained in performing the modeling step, the step of collecting and evaluating coordinates, the step of obtaining control parameter, and the step of establishing the occupation function into a database, thereby allowing the robot arm to quickly evaluate whether a collision behavior will occur in subsequent execution of a task. If a collision will occur, the robot arm executes the step of the finding the obstacle avoiding posture to dodge obstacles. The invention uses a non-contact approach for anti-collision design, which can improve the shortcomings faced by the existing contact type anti-collision design.

Abstract: A positive current collector, a secondary battery, and an electrical device are provided. In some embodiments, the positive current collector includes: a support layer; and a conductive layer located on at least one surface of the support layer, where the conductive layer includes a first metal portion configured to connect to a tab, where, along a thickness direction of the conductive layer, the first metal portion includes at least three sublayers, and melting points of the at least three sublayers rise stepwise in ascending order of distance from the support layer. In the embodiments of this application, the first metal portion includes at least three sublayers, and the melting points of the at least three sublayers rise stepwise in ascending order of distance from the support layer, thereby helping increase a bonding force between the conductive layer and the support layer and reducing the probability of peel-off and delamination between the layers.

Abstract: A network performance parameter sending method includes: obtaining, by a first network node, a segment identifier of a second network node in a segment list of a packet, where the second network node is a next-hop segment node of the first network node on a forwarding path of the packet; and adding, by the first network node, a network performance parameter of the first network node to the segment list, and then sending the packet to the second network node. In a process of forwarding the packet by using the segment list in the packet, the first network node uses the segment list to carry the network performance parameter of the network node.

Abstract: A method for estimating a time of arrival based on non-contiguous spectrums and an apparatus are provided. The method includes: receiving a plurality of signals from a transmit end on a plurality of frequency bands; determining, based on the plurality of signals, channel frequency responses CFRs of the frequency bands corresponding to the plurality of signals; determining a CFR of full bandwidth based on the CFRs of the frequency bands corresponding to the plurality of signals, where the full bandwidth includes the plurality of frequency bands; and determining a time of arrival estimate based on the CFR of the full bandwidth, where the time of arrival estimate is used to determine location information of a terminal device.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: Electronic telecommunication articles are described comprising a crosslinked fluoropolymer layer. In typical embodiments, the crosslinked fluoropolymer layer is a substrate, patterned (e.g. photoresist) layer, insulating layer, passivation layer, cladding, protective layer, or a combination thereof. Also describes are methods of making an electronic telecommunications article and method of forming a patterned fluoropolymer layer. The fluoropolymer preferably comprises at least 80, 85, or 90% by weight of polymerized units of perfluorinated monomers and cure sites selected from nitrile, iodine, bromine, and chlorine. Illustrative electronic communication articles include integrated circuits, printed circuit boards, antennas, and optical fiber cables. Fluoropolymer compositions are also described.

Abstract: This application provides a current collector and a preparation method thereof, a secondary battery containing such current collector, a battery module, a battery pack, and an electric apparatus. The current collector in this application includes a support layer, a binder layer, and a metal layer, where the binder layer is arranged between the support layer and the metal layer, the binder layer includes an organic binder and inorganic particles, a thickness D0 of the binder layer is 1.0-5.0 ?m, optionally 1.0-3.0 ?m; and the inorganic particles include large particles with a median particle size D50large and small particles with a median particle size D50small, and the median particle sizes of the large particles and the small particles satisfy the following relationships: D50large>D50small; D50large=(0.5-0.9)×D0; and D50small=(0.1-0.4)×D0.

Abstract: The embodiments of the present disclosure relate to an audio data processing method and apparatus, and a device and a storage medium. The method comprises: acquiring a first play position of first audio data, and an audition instruction of a user for a first sound effect; adding the first sound effect to a first audio clip in the first audio data, generating sound effect audition data and playing same; and if a first addition instruction of the user for a second sound effect is received, according to information of a first addition length carried in the first addition instruction, adding the second sound effect to a second audio clip, which takes the first play position as a start position, in the first audio data, so as to obtain second audio data. By means of the solution provided in the embodiments of the present disclosure, a sound effect addition operation can be simplified, sound effect addition results are enriched, and the user experience is also enhanced.

Abstract: Systems and methods of the present disclosure are directed to a method for predicting semantic similarity between documents. The method can include obtaining a first document and a second document. The method can include parsing the first document into a plurality of first textual blocks and the second document into a plurality of second textual blocks. The method can include processing each of the plurality of first textual blocks and the second textual blocks with a machine-learned semantic document encoding model to obtain a first document encoding and a second document encoding. The method can include determining a similarity metric descriptive of a semantic similarity between the first document and the second document based on the first document encoding and the second document encoding.

Abstract: Disclosed are a computer-implemented method, a system, and a computer program product for system-level tunable parameter identification. Performance characteristic data for an application to be tuned can be obtained by one or more processing units. At least one system-level tunable parameter for the application to be tuned can be identified by one or more processing units based on the obtained performance characteristic data for the application to be tuned and a pattern between training performance characteristic data and a set of training system-level parameter-related correlation coefficients. The set of training system-level parameter-related correlation coefficients can be respective correlation coefficients of system-level tunable parameters with respect to at least one performance metric.

Abstract: A method for manufacturing a semiconductor structure includes forming a fin over a substrate, wherein the fin includes first semiconductor layers and second semiconductor layers alternating stacked. The method also includes forming an isolation feature around the fin, forming a dielectric feature over the isolation feature, forming a cap layer over the fin and the dielectric feature, oxidizing the cap layer to form an oxidized cap layer, forming source/drain features passing through the cap layer and in the fin, removing the second semiconductor layers in the fin to form nanostructures, and forming a gate structure wrapping around the nanostructures.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.