Patents by Inventor Cheng Li

Cheng Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379964
    Abstract: This application provides a binder composition. The binder composition includes a first fluoropolymer and a second fluoropolymer, where the first fluoropolymer includes polyvinylidene fluoride with a weight-average molecular weight of 5000000-9000000, and a weight-average molecular weight of the second fluoropolymer is not greater than 600000. Featuring good processability, this binder composition, even added in small amounts, can provide electrode plates with great adhesion force and improve the cycling performance of a battery.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Applicant: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Cheng LI, Zipeng ZENG, Huihui LIU, Jingming WANG
  • Publication number: 20240376181
    Abstract: Disclosed are a fully human bispecific antibody against SARS-COV-2 and a use thereof. Specifically, the present disclosure also relates to a vector and host cell expressing same, and a preparation and purification method therefor. The bispecific antibody has a broad-spectrum binding ability and neutralizing ability, and the bispecific antibody can be used in the preparation of drugs for treating or preventing diseases caused by SARS-COV-2 infection and in detection or diagnosis of COVID-19.
    Type: Application
    Filed: August 3, 2022
    Publication date: November 14, 2024
    Inventors: Yanling WU, Cheng LI
  • Publication number: 20240377284
    Abstract: A system and method for testing two-phase liquid cooling are disclosed. The system may include, a liquid storage tank; a power pump having an inlet in communication with an outlet of the liquid storage tank; a regenerator having a first loop and a second loop and a first regulating valve; a preheater and a second regulating valve; a liquid outlet port and a liquid outlet valve; a liquid inlet port and a liquid inlet valve; and a condenser having an inlet in communication with an outlet of the second loop.
    Type: Application
    Filed: March 2, 2022
    Publication date: November 14, 2024
    Inventors: Cheng TAO, Yalong WANG, Fan LIU, Xiaodong ZHOU, Shuai LI, Xingang YU
  • Publication number: 20240379744
    Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Ko-Cheng Liu, Ming-Shuan Li, Ming-Lung Cheng, Chang-Miao Liu
  • Publication number: 20240379797
    Abstract: In an embodiment, a device includes: a first insulating fin; a second insulating fin; a nanostructure between the first insulating fin and the second insulating fin; and a gate structure wrapping around the nanostructure, a top surface of the gate structure disposed above a top surface of the first insulating fin, the top surface of the gate structure disposed below a top surface of the second insulating fin.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Cheng-Wei Chang, Shahaji B. More, Yi-Ying Liu, Shuen-Shin Liang, Sung-Li Wang
  • Publication number: 20240379422
    Abstract: A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Sheng-Tsung WANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Sung-Li WANG, Chih-Hao WANG
  • Publication number: 20240377732
    Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes a chemical formula of MaXbLc, where M is a metal, X is a multidentate aromatic ligand that includes a pyrrole-like nitrogen and a pyridine-like nitrogen, L is an extreme ultraviolet (EUV) cleavable ligand, a is between 1 and 2, b is equal to or greater than 1, and c is equal to or greater than 1.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Patent number: 12143681
    Abstract: Disclosed are a control method for focus movement on an EPG user interface and a display device. The method includes: displaying a television broadcast program on a display screen; receiving an instruction for displaying an EPG user interface, and displaying the EPG user interface on the display screen in response to the instruction; and receiving an instruction for indicating the movement of a focus along a channel arrangement direction in the EPG user interface, and in response to the instruction, determining a new position to which the focus moves in a target television channel according to the position of a pre-selected reference broadcast program, so as to control the focus to move to a target broadcast program corresponding to the new position.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: November 12, 2024
    Assignee: HISENSE VISUAL TECHNOLOGY CO., LTD.
    Inventors: Cheng Yang, Mengyuan Li
  • Patent number: 12140660
    Abstract: A detection system and a detection method are provided. The detection method includes configuring a processing circuit to perform an initialization phase, which includes: executing a detection process to respectively accumulate numbers of times that objects are detected to be present in sub-areas, so as to generate initial count values; and configuring the processing circuit to perform a normal operation phase, which includes: executing the detection process to respectively accumulate numbers of times that the objects are detected to be present in the sub-areas, so as to generate current count values corresponding to the sub-areas; and comparing the current count value with the initial count value in a current sub-area of the sub-areas. In response to the current count value being greater than the initial count value plus a first count threshold, a new stationary object is determined to be present in the current sub-area.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: November 12, 2024
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Modick Bahadur Basnet, Chi-Cheng Kuo, Jeng-Da Li
  • Publication number: 20240372759
    Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
  • Publication number: 20240368472
    Abstract: A surfactant composition includes 60 wt % or greater of a surfactant based on a total weight of the surfactant composition and 0.01 wt % to 5 wt % of a hydroxyl amine having structure (I) based on the total weight of the surfactant composition, wherein R1, R2 and R3 of Structure (I) are independently selected from the group consisting of H, an alkanolamine, or a hydroxyl alkyl group with linear or branched carbon chain having from 1 to 8 carbons, and R4 of Structure (I) is selected from the group consisting of an alkanolamine, or a hydroxyl alkyl group with linear or branched carbon chain having from 1 to 8 carbons.
    Type: Application
    Filed: October 6, 2021
    Publication date: November 7, 2024
    Inventors: Cheng Shen, Haiying Li, Shaoguang Feng, Jian Zou, Wanglin Yu
  • Publication number: 20240370670
    Abstract: A data processing system for conditioning productivity application file content for ingestion by an artificial intelligence (AI) language model includes a server system hosting a conversion service, the server system comprising processing and memory resources; an Application Programming Interface (API) for the conversion service to receive productivity application files at any scale; and a format converter of the conversion service, the format converter converting a productivity application file to a format compatible with the AI language model to enable the AI language model to operate on the file content based on a user instruction submitted with the file content as output by the format converter.
    Type: Application
    Filed: May 2, 2023
    Publication date: November 7, 2024
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Prerana Dharmesh GAMBHIR, Chandrasekar BALACHANDRAN, David PREJBAN, Aynoor SALEEM, Erali Jatin SHAH, Feng LI, Ziyu YI, Cheng XIANG, Apoorva Ajit DHAKRAS
  • Publication number: 20240372000
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20240373628
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Inventors: Wen-Tuo Huang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
  • Publication number: 20240371987
    Abstract: A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Chi-Fu LIN, Cheng-Hsin CHEN, Ming-I HSU, Kun-Ming HUANG, Chien-Li KUO
  • Publication number: 20240371887
    Abstract: A thin film transistor includes a first active layer, a second active layer, a first electrode, a second electrode and a third electrode. The first active layer includes a first surface away from a substrate. The second active layer includes a second surface in contact with the first surface. The first electrode, the first active layer and the second active layer have an overlapping region. The second electrode, the first active layer and the second active layer have an overlapping region. The third electrode, the first active layer and the second active layer have an overlapping region, and the third electrode is opposite to the second electrode. The second surface is located within the first surface, and a distance between at least part of a border of the second surface and a border of the first surface is less than or equal to 0.5 ?m.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuhang LU, Fengjuan LIU, Hehe HU, Zhengliang LI, Ce NING, Guangcai YUAN, Dandan ZHOU, Cheng XU
  • Publication number: 20240371769
    Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Cheng SHIH, Chia Cheng CHOU, Chun-Te LI
  • Patent number: 12137282
    Abstract: An image obtaining method includes outputting an image in at least one of multiple image output modes. The multiple image output modes include a full-size mode, a first binning mode, and a second binning mode. In the full-size mode, a first image is obtained according to a first pixel value. In the first binning mode, a second image is obtained according to a second pixel value and a third pixel value. In the second binning mode, a third image is obtained according to a fourth pixel value and a fifth pixel value.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: November 5, 2024
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Cheng Tang, Longjia Li, Gong Zhang
  • Patent number: 12137597
    Abstract: The present application provides a displaying base plate and a displaying device, which relates to the technical field of displaying. The displaying device can ameliorate the problem of screen greening caused by electrostatic charges, thereby improving the effect of displaying. The displaying base plate includes an active area and a non-active area connected to the active area, the non-active area includes an edge region and a first-dam region, and the first-dam region is located between the active area and the edge region; the displaying base plate further includes: a substrate; an anti-static layer disposed on the substrate, wherein the anti-static layer is located at least within the edge region; and a driving unit and a touch unit that are disposed on the substrate, wherein the driving unit is located within the active area.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: November 5, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yu Zhao, Yong Zhuo, Wei He, Yanxia Xin, Qun Ma, Xiping Li, Jianpeng Liu, Kui Fang, Cheng Tan, Xueping Li, Yihao Wu, Xiaoyun Wang, Haibo Li, Xiaoyan Yang
  • Patent number: 12136887
    Abstract: The present invention provides a multi-active bridge converter.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: November 5, 2024
    Assignee: Eaton Intelligent Power Limited
    Inventors: Jiajie Duan, Jianxiong Yu, Qiang Chen, Han Li, Cheng Luo, Dongsheng Li