Patents by Inventor Cheng Lin

Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149211
    Abstract: A chip resistor includes a substrate, first to fourth electrodes, a resistance layer, a resin electrode layer, first and second insulating protective layers, and first and second external electrode layers. The first and second electrodes are respectively disposed on two opposite edge areas of a front surface of the substrate. The resistance layer extends from the first electrode to the second electrode. The first insulating protective layer completely covers the resistance layer. The resin electrode layer includes first to third portions respectively covering the first and second electrodes, and a portion of the first insulating protective layer. The second insulating protective layer completely covers the third portion and partially covers the first and second portions. The third and fourth electrodes are disposed on a back surface of the substrate. The first and second external electrode layers respectively connect the first and third electrodes, and the second and fourth electrodes.
    Type: Application
    Filed: December 18, 2023
    Publication date: May 8, 2025
    Inventors: Shen-Li HSIAO, Po-Hsun SHIH, Kuang-Cheng LIN
  • Publication number: 20250149798
    Abstract: A system having a Reconfigurable ReflectArray (RRA) structure includes a radiation layer and a control layer. The radiation layer includes at least one P-Intrinsic-N (P-I-N) diode and a plurality of reconfigurable reflective units. At least one part of the reconfigurable reflective units is electrically connected to the at least one P-I-N diode. The control layer includes at least one switch element and at least one control unit. The at least one switch element is electrically connected to the radiation layer. The at least one control unit is electrically connected to the at least one switch element. The number of the reconfigurable reflective units is different from the number of the at least one switch element.
    Type: Application
    Filed: July 2, 2024
    Publication date: May 8, 2025
    Inventors: Shih-Cheng LIN, Sheng-Fuh CHANG, Chia-Chan CHANG, Yuan-Chun LIN, Ting-Hao SHIN
  • Publication number: 20250144150
    Abstract: The present invention provides a preparation method of pharmaceutical composition for treating chronic stroke, involving injection via brain into the cranium of a patient having chronic stroke for six months or more; the pharmaceutical composition is a suspension at least comprising adipose-derived stem cells treated by cell expansion, an active synergistic component and a growth factor, wherein the expression level of CD34 and CD45 of the adipose-derived stem cells treated by cell expansion is 10% or less, and the expression level of CD90 and CD105 is 90% or more; the active synergistic component is an extracellular vesicle; the growth factor is at least one selected from the group consisting of HGF, G-CSF, Fractalkine, IP-10, EGF, IL-1?, IL-1?, IL-4, IL-5, IL-13, IFN?, TGF? and sCD40L. The present invention overcomes the limitations of previous cell therapy and provides a cell-based preparation that is clinically safe and therapeutically effective for chronic cerebral stroke.
    Type: Application
    Filed: January 8, 2025
    Publication date: May 8, 2025
    Inventors: Po-Cheng Lin, Pi-Chun Huang, Chia-Hsin Lee, Ming-Hsi Chuang, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang, Yi-Chun Lin, Yu-Chen Tsai, Peggy Leh Jiunn Wong, Ruei-Yue Liang
  • Publication number: 20250151394
    Abstract: A device includes first to third power/ground (PG) elements; a first set of at least three tracks between the first and second PG elements and a second set of at least three tracks between the second and third PG elements, the tracks being arranged in equal numbers between the first and second PG and second and third PG elements; a first row of cells overlapping the first set; and a second row of cells overlapping the second set. In the first row of cells, a first cell has a first height and a second cell has a greater height than the first height; in the second row of cells, a third cell has the first height and a fourth cell has a lesser height less than the first height; and a track configured as an in-cell PG track is aligned with a boundary of the second and fourth cells.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Inventors: Ching-Yu HUANG, Wei-Cheng TZENG, Wei-Cheng LIN, Chia-Tien WU, Ken-Hsien HSIEH, Jiann-Tyng TZENG
  • Patent number: 12295191
    Abstract: A light emitting-diode (LED) display device is provided. The display device comprises plural pixels arranged in array and each pixel includes at least one LED chip. The LED chip is disposed at a cavity of a black matrix (BM) layer and electrical connected to a transistor of a circuit substrate, wherein the transistor is below the BM layer.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: May 6, 2025
    Assignee: VISIONLABS CORPORATION
    Inventors: Hung-Cheng Lin, Hung-Kuang Hsu, Hua-Chen Hsu
  • Patent number: 12292826
    Abstract: A method for managing a memory apparatus including a non-volatile (NV) memory element having a plurality of physical blocks includes: obtaining a first host address and first data from a first access command; obtaining a second host address and second data from a second access command; linking the first host address to a first page of the physical block and the second host address to a second page of the physical block; storing the first data and second data into the physical block; building a valid page position table and storing the valid page position table in the volatile memory; and building a global page address linking table and storing the global page address linking table in the volatile memory. The valid page position table and the global page address linking table are loaded from the volatile memory and stored to the NV memory element at predetermined time periods.
    Type: Grant
    Filed: May 14, 2024
    Date of Patent: May 6, 2025
    Assignee: Silicon Motion, Inc.
    Inventors: Tsai-Cheng Lin, Chun-Kun Lee
  • Publication number: 20250142968
    Abstract: A stretchable pixel array substrate, including a base and a component layer, is provided. The base has multiple first openings and multiple second openings. Each of the first openings has a first opening extending direction. Each of the second openings has a second opening extending direction. The first opening extending direction and the second opening extending direction are different. The first openings and the second openings are alternately arranged in a first direction and a second direction to define multiple islands and multiple bridges of the base. The component layer is disposed on the base and includes multiple island portions and multiple bridge portions. The island potions have multiple pixel structures and are respectively disposed on the islands of the base. The bridge portions have conductive wires and are respectively disposed on the bridges of the base. The conductive wires are electrically connected to the pixel structures.
    Type: Application
    Filed: December 29, 2024
    Publication date: May 1, 2025
    Applicant: AUO Corporation
    Inventors: Yun-Wen Pan, Kung-Cheng Lin
  • Publication number: 20250140450
    Abstract: A chip resistor includes a substrate, first and second conductive structures in the substrate, first to third front electrodes and first to third back electrodes respectively on front and back surfaces of the substrate, first and second resistance layers respectively on the front and back surfaces, and first and second external electrode layers. The first to third front electrodes are opposite to the first to third back electrodes. The first back electrode and the first front electrode are connected to the first conductive structure. The first resistance layer is connected to the second front electrode and the second conductive structure. The second resistance layer is connected to the first and third back electrodes and the first and second conductive structures. The first and second external electrode layers respectively connect the first front electrode and the first back electrode, and the second front electrode and the second back electrode.
    Type: Application
    Filed: December 6, 2023
    Publication date: May 1, 2025
    Inventors: Shen-Li HSIAO, Po-Hsun SHIH, Kuang-Cheng LIN
  • Publication number: 20250136661
    Abstract: The present disclosure provides a pharmaceutical composition including an adipose tissue-derived extracellular vesicle and a biologic, and a use of the pharmaceutical composition for treating arthritis. The pharmaceutical composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.
    Type: Application
    Filed: December 1, 2023
    Publication date: May 1, 2025
    Inventors: Hsiu-Jung Liao, Ssu-Jung Lu, Yu-Chen Tsai, Po-Cheng Lin, Ming-Hsi Chuang
  • Patent number: 12288814
    Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.
    Type: Grant
    Filed: January 24, 2024
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Patent number: 12288785
    Abstract: An integrated circuit includes a horizontal routing track in a first metal layer, and a backside routing track in a backside metal layer. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. The horizontal routing track is conductively connected to a first terminal of a first transistor without passing through a routing track in another metal layer. The backside routing track is conductively connected to a second terminal of the first transistor without passing through a routing track in another metal layer. One of the first terminal and the second terminal is a gate terminal of the first transistor while another one the first terminal and the second terminal is either a source terminal or a drain terminal of the first transistor.
    Type: Grant
    Filed: February 1, 2024
    Date of Patent: April 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-An Lai, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Publication number: 20250127829
    Abstract: The present disclosure provides a method for preventing and/or repairing ocular cell damage by using a Streptococcus thermophilus iHA318 strain and its metabolites.
    Type: Application
    Filed: October 18, 2024
    Publication date: April 24, 2025
    Inventors: Meei-Yn Lin, Pin-Chao Huang, Pei-Cheng Lin, Yi-Wen Chen, Chin-Hsiu Yu, Shao-Yu Lee, Tsung-Han Lu
  • Publication number: 20250129316
    Abstract: This disclosure relates to a biological tissue forming method includes the following steps: providing a biological tissue forming package with a base, a membrane, a sliding assembly and a sealing film that seals a chamber of the base used for receiving the membrane and the sliding assembly with one of the base and the sealing film being light-transmitting; passing a biological tissue fluid through the sealing film and the sliding assembly so as to be dispensed on the membrane; moving the sliding assembly away from a covering position used for covering the membrane via at least one passive magnetic element so as to expose the biological tissue fluid on the membrane; and emitting the biological tissue fluid exposed on the membrane by a curing light transmitting through the one of the base and the sealing film so as to cure the biological tissue fluid into a biological tissue.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 24, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chao-Hong HSU, Teng-Yen WANG, Yang-Cheng LIN, Hsin-Yi HSU, Yu-Bing LIOU, Chang-Chou LI, Chih-Hung HUANG, Tung-Ying LIN, Li-Hsin LIN, Yuchi WANG, Hsin-Hsin SHEN
  • Patent number: 12282179
    Abstract: An image compensation device and a prism carrying mechanism thereof. The prism carrying mechanism comprises a base and a pair of prism carrying members. The base comprises a base body, a light passing hole disposed at the base body, and a plurality of first sliding assembling parts integrally formed on the same side of the base body. Each of the prism carrying members comprises a carrying member body, a prism assembling part disposed at the carrying member body and corresponding to the light passing hole, and a plurality of second sliding assembling parts integrally formed on the same side of the carrying member body. The prism assembling parts of the pair of prism carrying members are oppositely and alternately disposed in an axial direction. The plurality of second sliding assembling parts are slidably assembled to the plurality of first sliding assembling parts respectively.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: April 22, 2025
    Assignee: LUXSHARE-ICT CO., LTD
    Inventors: Fu-Yuan Wu, Chun-Hui Wu, Shang-Yu Hsu, Meng-Ting Lin, Yu-Cheng Lin
  • Patent number: 12283546
    Abstract: An integrated circuit includes a strip structure having a front side and a back side. The integrated circuit includes a gate structure on the front side of the strip structure. The integrated circuit includes an isolation structure surrounding the strip structure. The integrated circuit includes a backside via in the isolation structure. The integrated circuit includes a contact over the strip structure, wherein a first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and in contact with the backside via.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: April 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Wei-Cheng Lin, Cheng-Chi Chuang, Jiann-Tyng Tzeng
  • Patent number: 12282630
    Abstract: The invention provides a touch display device and an operation method for the touch display device. The touch display device includes an integrated control circuit and a touch driver. The integrated control circuit is coupled to the touch driver. The integrated control circuit outputs a first synchronization signal to the touch driver. The touch driver outputs a touch mode signal to the integrated control circuit, so that the integrated control circuit generates a synchronization enabling signal to the touch driver according to the touch mode signal.
    Type: Grant
    Filed: December 21, 2023
    Date of Patent: April 22, 2025
    Assignee: E Ink Holdings Inc.
    Inventors: Hung Wei Tseng, Yi Chun Kuo, Chen Cheng Lin
  • Patent number: 12284005
    Abstract: A reconfigurable intelligent surface includes a radiant layer, a sensing feeding circuit layer, a processing layer and a controlling circuit layer. The radiant layer includes at least two antennas and a plurality of reflecting units. Each of the at least two antennas is configured for sensing a polarization, a frequency or a direction angle of an incident electromagnetic wave. The reflecting units are arranged to form a reflecting surface. The sensing feeding circuit layer is signally connected to the antennas. The processing layer is signally connected to the sensing feeding circuit layer, and the processing layer is configured to produce a controlling signal corresponding thereto. The controlling circuit layer is signally connected to the radiant layer and the processing layer, wherein the controlling circuit layer receives the controlling signal and controls the reflecting units according to the controlling signal to adjust and form a reflecting electromagnetic wave.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: April 22, 2025
    Assignee: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Chia-Chan Chang, Sheng-Fuh Chang, Shih-Cheng Lin, Yuan-Chun Lin, Wei-Lun Hsu
  • Patent number: 12282635
    Abstract: A touch display device includes a substrate, a display element layer, a composite substrate, a touch electrode and an adhesive layer. The display element layer is disposed on the substrate. The composite substrate includes a support layer and a moisture barrier layer. The moisture barrier layer is in direct contact with and covers a surface of the support layer. The display element layer is located between the substrate and the composite substrate. A moisture transmission rate of the moisture barrier layer is less than 1×10?2 g/m2/day. The touch electrode is disposed on the composite substrate. The adhesive layer is disposed between the display element layer and the composite substrate.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: April 22, 2025
    Assignee: E Ink Holdings Inc.
    Inventors: Chen Cheng Lin, Hung Wei Tseng, Yi Chun Kuo, Fang Chia Hu
  • Patent number: 12283481
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes a step of performing a chemical mechanical polishing process on a first silicon oxide layer to form a planar surface layer; surface treatment is performed on the planar surface layer to form a treated planarization layer, and a second silicon oxide layer is formed on the treated planarization layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 22, 2025
    Assignee: United Microelectronics Corp.
    Inventors: Yu Cheng Lin, Wei-Chuang Lai
  • Publication number: 20250125293
    Abstract: A semiconductor package includes a substrate including: a substrate comprising a through-hole; a first semiconductor chip in the through-hole; an adhesive layer on a side surface of the first semiconductor chip in the through-hole; a first redistribution structure on an upper surface of the substrate and bonded and connected to the substrate; a second redistribution structure on a lower surface of the substrate and bonded and connected to the substrate; a second semiconductor chip on the first redistribution structure; and a through-via spaced apart from the first semiconductor chip in a horizontal direction and passing through the substrate in a vertical direction.
    Type: Application
    Filed: July 30, 2024
    Publication date: April 17, 2025
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jing Cheng LIN, Youngkun JEE