Abstract: Iron oxide particles which have a polyhedral shape and which contain molybdenum. The crystallite size of the plane of the iron oxide particles is preferably 280 nm or more. Furthermore, a method for producing the iron oxide particles. The method includes calcining an iron compound in the presence of a molybdenum compound.

Abstract: Embodiments of the present disclosure relate to the semiconductor field, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, first gates and second gates, and a first conductive channel; where the substrate includes first active regions and two second active regions located between adjacent first active regions, the first active region defines a pull-down transistor, the second active region defines a pull-up transistor; the first active region has a first source region, a first channel region, and a first drain region arranged along a second direction.

Abstract: It relates to tantalum oxide particles containing molybdenum. The tantalum oxide particles preferably have a polyhedral shape, and the crystallite size of the tantalum oxide particles at 2?=22.8° is preferably 160 nm or more. It also relates to a method for producing the tantalum oxide particles, the method including firing a tantalum compound in the presence of a molybdenum compound.

Abstract: A semiconductor structure includes: a substrate, a first conductive layer disposed on the substrate, a second conductive layer disposed on a surface of the first conductive layer away from the substrate, and third conductive layers covering side walls of the first conductive layer and in contact with the second conductive layer. Contact resistance between the third conductive layers and the second conductive layer is less than contact resistance between the first conductive layer and the second conductive layer.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance.

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Abstract: An electrostatic discharge protection structure for a nitride-based device having an active region, an electrostatic discharge protection region outside the active region for forming the electrostatic discharge protection structure, and a field plate formed in the active region is provided. The electrostatic discharge protection structure includes a channel layer, and a barrier layer, a first p-type nitride layer and a metal layer formed on the channel layer in such order. The metal layer is electrically connected to the field plate in the active region. A nitride-based device having the electrostatic discharge protection structure and a method for manufacturing a nitride-based device is also disclosed.

Abstract: An operation sequence adding method, an electronic device, and a system are provided. The method includes: detecting a first operation performed by a user on a first control; obtaining an event type of the first operation and name information of a first application in response to the first operation; displaying a second interface of the first application in response to the first operation, and detecting a second operation performed by the user on a second control; obtaining a second control identifier and an event type of the second operation in response to the second operation; saving the name information of the first application, the second control identifier, and the event type of the second operation; displaying a third interface of a second application, where the third interface of the second application includes a third control; detecting a third operation performed by the user on the third control; and displaying the second interface of the first application in response to the third operation.

Abstract: The present disclosure relates to semiconductor device with a multi-gate structure. The semiconductor device includes a substrate and a doped region disposed within the substrate. A gate electrode is disposed over the doped region, and a source region and a drain region are disposed within the doped region. A shallow trench isolation (STI) structure is disposed within the substrate and laterally surrounds the source region and the drain region. A first doped liner is disposed along the STI structure, where the first doped liner separates the STI structure from the source region and the drain region. A second doped liner is disposed along the STI structure, where the second doped liner is separated from the first doped liner by the STI structure above a bottom surface of the STI structure.

Abstract: Techniques for hierarchical core valid tracking are described. An example apparatus comprises a cache to store information accessible by two or more cores, and circuitry coupled to the cache to maintain coherence of the information stored in the cache and to hierarchically track respective associations of the information stored in the cache with the two or more cores, where a lowest hierarchical level of the hierarchically tracked associations is to indicate a logical core identifier of a particular core of the two or more cores. Other examples are disclosed and claimed.

Abstract: The present disclosure provides for the preparation and use of immunostimulatory conjugate complexes for targeted delivery and activation. In particular, the present disclosure provides compounds represented by the formula MI-S-C-A for use as linker, and drug-linked pharmaceutical compounds represented by the formula MI-S-C-A-D. The pharmaceutical compounds of the present disclosure have improved water solubility, reduced cytotoxicity, and enhanced pharmaceutical activity.

Abstract: The present disclosure relates to detection circuits, touch control panels and electronic apparatuses. The circuit includes: a charge amplifier including a first input terminal, a second input terminal and an output terminal; a feedback capacitor, both ends of which are electrically connected to the first input terminal and the output terminal respectively, wherein the feedback capacitor is in parallel connection with a first switch; and a sensor electrode electrically connected to the first input terminal. A first excitation signal is applied to a thin film transistor (TFT) in a touch control panel where the detection circuit is located. A second excitation signal is applied to the second input terminal, wherein the first excitation signal is in-phase with the second excitation signal. An amplitude of the first excitation signal is larger than an amplitude of the second excitation signal.

Abstract: A process detection system for rack and server in rack is disclosed. In the system, a detection device performs a server process detection of L10 stage on servers in a rack, and performs a rack process detection of L11 stage; when the detection device detects that a server in the rack fails in a server process during the server process detection of L10 stage or that the rack fails in a rack process during the rack process detection of L11 stage, the server is repaired, or replaced by a backup server. Before the detection flow is performed continuously, the server process detection of L10 stage is performed on the repaired server, or the backup server not performing the server process detection of L10 stage yet, and then. The detection flow can be performed continuously on the backup server which has performed the server process detection of L10 stage.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

Abstract: An automatic control system for a phase angle of a motor is provided. A current detector circuit detects a current signal of the motor to output a current detected signal. A control circuit outputs a control signal according to the current detected signal indicating a time point at which the current signal reaches a zero value. A driver circuit outputs a driving signal according to the control signal. An output circuit operates to output a motor rotation adjusting signal to the motor to adjust a rotational state of the motor according to the driving signal.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: A method for replacing an identity certificate in a blockchain network includes a service subnet, a consensus subnet, and a routing layer used for isolating the service subnet from the consensus subnet. The method includes: receiving a root certificate replacement notification transmitted by a certificate authentication center; obtaining a public key corresponding to the certificate authentication center; verifying the root certificate replacement notification by using the obtained public key; forwarding the root certificate replacement notification to a consensus node in the consensus subnet after the validation succeeds, so that the consensus node records the root certificate replacement notification into a latest data block after a consensus on the root certificate replacement notification is reached; and requesting, when the data block is received, the certificate authentication center to replace an identity certificate.

Abstract: A parallel-type coating apparatus for coating at least one object to be coated carried by a carrier includes a double-layer vacuum chamber having feed and discharge chambers opposite to each other in a Z-direction, and a plurality of process chambers for performing at least a fixed point coating on the at least one object to be coated. The double-layer vacuum chamber and the process chambers are arranged in two juxtaposed rows in a Y-direction transverse to the Z-direction. A feed lifting mechanism is disposed in one of the double-layer vacuum chamber 3 and the process chambers, and includes a feed lifting seat movable in the Z-direction. A plurality of first conveying devices are respectively disposed in the other ones of the process chambers for conveying the carrier. A method for coating a multilayer film on at least one object to be coated carried by a carrier is also disclosed.

Abstract: An automatic control system for a phase angle of a motor is provided. A current detector circuit detects a current signal of the motor to output a current detected signal. A control circuit outputs a control signal according to the current detected signal indicating a time point at which the current signal reaches a zero value. A driver circuit outputs a driving signal according to the control signal. An output circuit operates to output a motor rotation adjusting signal to the motor to adjust a rotational state of the motor according to the driving signal.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a substrate, and forming a first isolating layer, a first stabilizing layer, a second isolating layer and a second stabilizing layer, which are sequentially stacked onto one another, on the substrate; forming a through hole penetrating through the first isolating layer, the first stabilizing layer, the second isolating layer and the second stabilizing layer, and forming a lower electrode on a side wall and a bottom portion of the through hole; removing a portion of a thickness of the second stabilizing layer to expose a portion of the lower electrode; forming a mask layer on a side wall of the exposed lower electrode; and etching the second stabilizing layer by using the mask layer as a mask to form a first opening.