Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming source/drain doping regions in the base substrate at two sides of each of the gate structures; forming an interlayer dielectric layer over the base substrate and the source/drain doping regions; forming a mask layer having a plurality of first openings there-through and over the interlayer dielectric layer, the first opening having a first length; performing a surface treatment process to remove portions of the mask layer from the first openings and to increase the first length of the first openings; forming contact through holes passing through the interlayer dielectric layer and exposing the source/drain doping regions using the mask layer with the first openings having the increased first length as an etching mask; and forming a contact via in each of the contact through holes.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate including a device region and a peripheral region. The base substrate includes a base interconnection structure. The method also includes forming a medium layer on the base substrate. In addition, the method includes forming a first trench having a first depth in the peripheral region, and forming a second trench having a second depth in the device region. The second depth is greater than the first depth. Moreover, the method includes forming a first opening in the device region and forming a second opening in the peripheral region. Further, the method includes forming a first interconnection structure by filling the first opening with a conductive material and forming a second interconnection structure by filling the second opening with the conductive material.

Abstract: The present disclosure is related to an optoelectronic device comprising a semiconductor stack comprising a first surface and a second surface opposite to the first surface; a first contact layer on the first surface; and a second contact layer on the second surface, wherein the second contact layer is not overlapped with the first contact layer in a vertical direction; wherein the second contact layer comprises a plurality of dots separating to each other and formed of semiconductor material.

Abstract: A method includes providing a semiconductor structure including an active region having a first doped region, a first contact member on the first doped region, first and second gates on opposite sides of the first contact member, an interlayer dielectric layer surrounding the first and second gates and the first contact member. The method also includes forming a first insulator layer having first and second contact holes, forming a second insulator layer on sidewalls of the first and second contact holes, filling the first and second contact holes with a first conductive material to form first and second contacts to the first and second gates, forming a third insulator layer on the first and second contacts, selectively etching the first insulator layer to form a third contact hole, and filling the third contact hole with a second conductive material to form a third contact to the first contact member.

Abstract: A semiconductor device and fabrication method thereof are provided. The method includes forming at least one dummy gate structure and sidewall spacers of the dummy gate structure in a first dielectric layer, together on a substrate, and removing the dummy gate structure, thereby forming a first opening between the sidewall spacers. The method further includes forming a gate structure in the first opening and having a top surface levelled the first dielectric layer, removing a portion of the sidewall spacers and a portion of the gate structure, respectively, to form a second opening in the first dielectric layer, on remaining sidewall spacers, and on remaining gate structure, and forming a capping layer to fill the second opening and to have a top surface levelled with the first dielectric layer.

Abstract: An etching method and a fabrication method of semiconductor structures are provided. The etching method includes forming trenches in a to-be-etched structure, and forming a dielectric layer in the trenches. The etching method further includes etching the dielectric layer in the trenches by an etching process, and controlling at least an etching temperature of the etching process while a polymer is formed on side surface of the to-be-etched structure. During the etching process of the dielectric layer, the polymer undergoes a deposition stage and a removal stage. The deposition stage has a deposition rate of the polymer greater than an etch rate of the polymer, and the removal stage has the deposition rate of the polymer less than the etch rate of the polymer.

Abstract: A grid gateway and a transmission tower management system having a plurality of the grid gateways are disclosed. The grid gateways are connected with one another to form a mesh network. A plurality of sensors are provided within a wireless transmission range of the grid gateways. The sensors collect and send environmental parameters to the corresponding grid gateway within the wireless transmission range, in order to choose an optimal transmission path in the mesh network through grid gateways to transmit. The environmental parameters are transmitted through the optimal transmission path to a server for storage and analysis. A grid gateway and a transmission tower management system having a plurality of the grid gateways have broad and local area wireless transmission ability, so as to overcome restrictions of topography and communication to execute broad area management and monitor tasks.

Abstract: Methods for forming semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a hard mask structure over a substrate and etching the substrate through an opening of the hard mask structure to form a trench. The method for manufacturing a semiconductor structure further includes removing a portion of the hard mask structure to enlarge the opening and forming an epitaxial-growth structure in the trench and the opening.

Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.

Abstract: An adjusting method and device of focusing curve of camera lens is disclosed. Steps of the adjusting method of focusing curve of camera lens includes: determining an adjustable moving range; moving the camera lens in the area of adjustable moving range, and recording a high definition of the camera lens; computing a difference value of a initial position of the camera lens and the high definition of the camera lens, and computing a focus offset; adjusting the focusing curve according to the focusing curve. Therefore, the angle of the camera lens motor can be adjusted accurately.

Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.

Abstract: Disclosed are ways to generate a melody. Currently, no algorithm exists for automatically composing a melody based on music lyrics. However, according to some recent studies, within a song, there usually exists a correlation between a song's notes and a song's lyrics wherein a melody can be generated based on such correlation. Disclosed herein, are systems, methods and algorithms that consider the correlation between a song's lyrics and a song's notes to compose a melody.

Abstract: A video encoding device calculates number of frames into which the current image needs to be encoded. The video encoding device divides the current image into a plurality of macro blocks, identifies importance of the respective macro blocks according to content of the current image and ranks the macro blocks from high to low according to the assigned importance. The video encoding device labels each macro block with a label, and encodes the macro blocks according to its label to form frames.

Abstract: An embodiment method includes forming a first fin and a second fin over a semiconductor substrate. The first fin includes a first semiconductor strip of a first type, and the second fin includes a second semiconductor strip of the first type. The method further includes replacing the second semiconductor strip with a third semiconductor strip of a second type different than the first type. Replacing the second semiconductor strip includes masking the first fin using a barrier layer while replacing the second semiconductor strip and performing a chemical mechanical polish (CMP) on the third semiconductor strip using a slurry that planarizes the third semiconductor strip at a faster rate than the barrier layer. In some embodiments, the method may further include depositing a sacrificial layer over a wafer containing the first and second fins and performing a non-selective CMP to substantially level a top surface of the wafer.

Abstract: A matching system includes at least one object matching apparatus and a search matching apparatus. Each object matching apparatus includes first antennas for emitting at least one radio frequency signal. The search matching apparatus includes a distance determination module having second antennas for receiving the radio frequency signal, and calculating a relative distance information and a relative direction information corresponding to each object matching apparatus according to a signal strength value of the radio frequency signal; a direction determination module for calculating an absolute direction information of the search matching apparatus corresponding to the earth coordinate system; and a calculating module for receiving the relative distance information, the relative direction information and the absolute direction information on the earth coordinate system to calculate an relative position corresponding to each object matching apparatus.

Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

Abstract: A data storing method for a rewritable non-volatile memory module and a memory controller and a memory storage device using the same are provided. The data storing method includes moving or writing data into a physical erase unit of the rewritable non-volatile memory module and determining whether the physical erase unit contains a dancing bit. The data storing method further includes when the physical erase unit contains the dancing bit, restoring the rewritable non-volatile memory module to the state before the data is moved or moving the data from the physical erase unit to another physical erase unit. Thereby, the data storing method can effectively ensure the reliability of the data.

Abstract: A method of forming a shallow trench isolation (STI) structure in a substrate includes forming a pad oxide layer over the substrate. The method includes forming a nitride-containing layer over the pad oxide layer, wherein the nitride-containing layer has a first thickness. The method further includes forming the STI structure extending through the nitride-containing layer, into the substrate. The STI structure has a height above a top surface of the pad oxide layer. The method includes establishing a correlation between the first thickness, the height of the STI structure above the top surface of the pad oxide layer, and an offset between the first thickness and the height of the STI structure above the top surface of the pad oxide layer. The method includes calculating the height of the STI structure above the pad oxide layer based on the correlation, and selectively removing a determined thickness of the STI structure.