Abstract: A display device driving method is provided. The display device driving method comprises the steps outlined below. A display device is provided, in which each of the first gate lines of a driving circuit of the display device has a first RC value and each of the second gate lines of the drive circuit has a second RC value smaller than the first RC value. A first gate driving signal having a first pulse width is generated to each of the first gate lines to drive corresponding first pixel rows. A second gate driving signal having a second pulse width is generated to each of the second gate lines to drive corresponding second pixel rows, wherein the second pulse width is smaller than the first pulse width.

Abstract: An exemplary protection circuit is provided to provide a controlled, latency-free, steady voltage. The circuit includes a switch module, an induction, a response module, a protection chip, and a sequence controller. The protection chip turns on the switch module when the voltage provided by a capacitor is less than a threshold voltage, thus the connection between the power supply device and the conversion circuit is enabled. The protection chip further outputs a high level signal to the sequence controller upon receiving an induction signal from the induction module. The sequence controller outputs a low level signal to the response module upon receiving the high level signal, to turn off a connection between the first end of the capacitor and ground, otherwise, a high signal is output to turn on the connection between the first end of the capacitor and ground.

Abstract: A TFT array manufacturing method is disclosed herein and includes steps: forming a first metal layer on a substrate; depositing a first insulating layer to cover the first metal layer; forming an oxide semiconductor layer on the first insulating layer in a TFT area; forming a second insulating layer on the first insulating layer and the oxide semiconductor layer; etching the second insulating layer in the TFT area to expose the oxide semiconductor layer and etching the second insulating layer and the first insulating layer in a signal wire area simultaneously to expose the first metal layer; and forming a second metal layer on the second insulating layer of the TFT area, and the second metal layer being connected the oxide semiconductor layer, and forming the second metal layer on the first metal layer of the signal wire area to contact the first metal, layer.

Abstract: A TFT array manufacturing method is disclosed herein and includes steps: forming a first metal layer on a substrate; depositing a first insulating layer to cover the first metal layer; forming an oxide semiconductor layer on the first insulating layer in a TFT area; forming a second insulating layer on the first insulating layer and the oxide semiconductor layer; etching the second insulating layer in the TFT area to expose the oxide semiconductor layer and etching the second insulating layer and the first insulating layer in a signal wire area simultaneously to expose the first metal layer; and forming a second metal layer on the second insulating layer of the TFT area, and the second metal layer being connected the oxide semiconductor layer, and forming the second metal layer on the first metal layer of the signal wire area to contact the first metal, layer.

Abstract: A delay protection circuit is installed between a power supply unit and a load of an electronic device, and includes a first capacitor and second capacitors. The delay protection circuit allows the supply of electric power to the load by the PSU, and detects power being output by the PSU. If the power output by the PSU exceeds a rated power of the load, the first capacitor becomes chargeable by the PSU, and the load is electrically disconnected from the PSU once a voltage on the first capacitor achieves a predetermined voltage level. The second capacitors are also available for charging by the PSU according to a difference between the power being output by the PSU and the rated power of the load to provide automatic adjustability of a delay time for the voltage on the first capacitor to achieve the predetermined voltage.

Abstract: The present invention provides a thin film transistor comprising at least a gate electrode formed on a substrate, and a gate insulating layer in contacting the gate electrode, and an oxide semiconductor layer deposited on the other side of the gate insulating layer. The concentration of hydrogen in the gate insulating layer has a gradient distribution, wherein the concentration of hydrogen adjacent the gate electrode is higher; and while the concentration of hydrogen adjacent the oxide semiconductor layer is lower. The present invention further provides a method for manufacturing a thin film transistor and an according thin-film-transistor liquid crystal display device.

Abstract: The present invention discloses a transistor, the preparation method thereof, and a display panel. The transistor comprises: a gate electrode; a gate insulating layer covering the gate electrode; an oxide semiconductor layer formed on the gate insulating layer; a first protective layer formed on the oxide semiconductor layer; a source/drain electrode connected with the oxide semiconductor layer; and a second protective layer covering the source/drain electrode; wherein, the hydrogen atom content per unit volume of the first protective layer is less than that of the gate insulating layer, and the hydrogen atom content per unit volume of the gate insulating layer is less than that of the second protective layer. Through the above solutions, the present invention can suppress the combination of the oxygen atom of the semiconductor layer in the transistor and the external hydrogen atom, to improve the performance and stability of the device.

Abstract: A display panel, a transistor and the manufacturing method thereof are disclosed. The manufacturing method includes: forming a first electrode, a first insulation layer, a sacrificial layer, and a second/third electrode metal layer on a substrate in turn; etching the second/third electrode metal layer to expose at least portions of the sacrificial layer; and dry-etching the at least portions of the exposed sacrificial layer to expose at least portions of the first insulation layer. The etching selectivity ratio of the sacrificial layer to the first insulation layer is larger than a first value when the conditions of the etching process are the same. The first value is larger than one, in this way, the stability and the electron mobility of the transistor are enhanced.

Abstract: An exemplary protection circuit is provided to provide a controlled, latency-free, steady voltage. The circuit includes a switch module, an induction, a response module, a protection chip, and a sequence controller. The protection chip turns on the switch module when the voltage provided by a capacitor is less than a threshold voltage, thus the connection between the power supply device and the conversion circuit is enabled. The protection chip further outputs a high level signal to the sequence controller upon receiving an induction signal from the induction module. The sequence controller outputs a low level signal to the response module upon receiving the high level signal, to turn off a connection between the first end of the capacitor and ground, otherwise, a high signal is output to turn on the connection between the first end of the capacitor and ground.

Abstract: An energy-efficient power control device, which employs a snubber circuit only during the risk of voltage spikes during fast switching, includes a buck converter, a power supply unit (PSU), a peak detecting circuit, a snubber circuit, and a logic circuit. The power control device supplies power to an input terminal of an electronic device. The snubber circuit is connected to the buck converter. The logic circuit is connected between the peak detecting circuit and the snubber circuit and determines whether the buck converter is under the heavy load or a light load according to the voltage, and connects the snubber circuit when the buck converter is under the heavy load, and disconnects the snubber circuit when the buck converter is under the light load.

Abstract: An exemplary electronic device includes a housing, a transparent touch display panel, electronic components, a storage unit, a power supply, and a processing unit. The transparent touch display panel is in a light permeable state when electrified by the power supply. The storage unit stores running information of the electronic components, and a lookup table. The lookup table records relationships between the electronic components and certain of the coordinates according to physical locations of the electronic components relative to the transparent touch display panel. The transparent touch display panel receives a user touch input in the light permeable state. The processing unit identifies coordinates associated with a location of the user touch input, determines which electronic component corresponds to the user touch input based on the lookup table, acquires the running information of the electronic component, and displays the acquired running information on the transparent touch display panel.

Abstract: The present invention discloses a thin film transistor and an active matrix flat display device, the thin film transistor comprising a gate electrode, a first insulating layer, a source electrode, a drain, and multiple oxide semiconductor layers, wherein, the multiple oxide semiconductor layers sequentially laminate between the source electrode, the drain electrode and the first insulating layer and comprise a first oxide semiconductor layer disposed close to the first layer and a second oxide semiconductor layer electrically connected with the source electrode and the drain electrode, and the resistivity of the first oxide semiconductor layer greater than 104 ?·cm, the resistivity of the second oxide semiconductor layer smaller than 1 ?·cm. Therefore, it ensures normal operation of the thin film transistor in order to ensure the display quality of the active matrix flat panel display device.

Abstract: The present invention discloses an active-matrix panel display device, a TFT and a method for forming the same The method includes that arranging a first insulating layer on a gate, stacking an oxide semiconductor layer and a buffer layer in order on the first insulating layer, arranging as source on the oxide semiconductor layer and a drain on the buffer layer, and plasma processing or heating in oxygen atmosphere the buffer layer which does not directly contact the source and the drain. Therefore, the present invention is capable of preventing the oxide semiconductor layer from damage in follow-up processes to assure stability of the TFT and display quality of the active-matrix panel display device.

Abstract: A power supply device includes a power supply unit, a buck converter, a logic circuit, and a snubber circuit. The buck converter and the logic circuit are connected to the power supply unit. The buck converter is configured to convert a direct current voltage output from the power supply unit into a preset voltage supplied to an input terminal of an electronic device. The snubber circuit is electronically connected between the buck converter and the logic circuit. The power supply unit determines whether the buck converter is under a heavy load or light load. If the buck converter is under the heavy load, the power supply unit triggers the logic circuit to allow the snubber circuit to connect to ground through the logic circuit. If the buck converter is under the light load, the power supply unit triggers the logic circuit to allow the snubber circuit to disconnect from ground.

Abstract: A display device driving method is provided. The display device driving method comprises the steps outlined below. A display device is provided, in which each of the first gate lines of a drive circuit of the display device has a first RC value and each of the second gate lines of the drive circuit has a second RC value smaller than the first RC value. A first gate driving signal having a first pulse width is generated to each of the first gate lines to drive corresponding first pixel rows. A second gate driving signal having a second pulse width is generated to each of the second gate lines to drive corresponding second pixel rows, wherein the second pulse width is smaller than the first pulse width.

Abstract: A delay protection circuit is installed between a power supply unit and a load of an electronic device, and includes a first capacitor and second capacitors. The delay protection circuit allows the supply of electric power to the load by the PSU, and detects power being output by the PSU. If the power output by the PSU exceeds a rated power of the load, the first capacitor becomes chargeable by the PSU, and the load is electrically disconnected from the PSU once a voltage on the first capacitor achieves a predetermined voltage level. The second capacitors are also available for charging by the PSU according to a difference between the power being output by the PSU and the rated power of the load to provide automatic adjustability of a delay time for the voltage on the first capacitor to achieve the predetermined voltage.

Abstract: A driver for driving a light emitting device includes an output stage and a driving stage. The output stage is for outputting a driving current to the light emitting device according to a driving signal, wherein the light emitting device is coupled between the output stage and a second reference voltage different from the first reference voltage. The driving stage is for generating the driving signal to the output stage, wherein one of the third reference voltage and the fourth reference voltage is within a range between the first reference voltage and the second reference voltage, and the other of the third reference voltage and the fourth reference voltage is outside the range between the first reference voltage and the second reference voltage.

Abstract: A source driver with low consumption and the driving method thereof are provided herein. The source driver includes an output buffer with a first input terminal receiving a pixel signal, a second input terminal, and an output terminal coupled to the second input terminal and a display panel. The source driver also includes a pre-charge circuit pre-charges a first terminal of the display panel to a first preset voltage or a second preset voltage for a pre-charge period according to a polarity of a common voltage coupled to the display panel. The second preset voltage is smaller than the first preset voltage. The output buffer is inactivated during the pre-charge period and activated for a preset period after the pre-charge period. Therefore, the present invention reduces power consumption of the source driver.

Abstract: A source driver adapted to drive a display panel and a driving method thereof are provided herein. The source driver includes an output buffer and a first pre-charge circuit. The output buffer has a first input terminal receiving a pixel signal and has both of a second input terminal and an output terminal coupled to the display panel. The first pre-charge circuit charges the output terminal of the output buffer to a preset voltage associated with the pixel signal for a pre-charge period. The output buffer is inactivated during the pre-charge period and is activated for a preset period after the pre-charge period. Therefore, power consumption of the source driver can be reduced.

Abstract: A liquid crystal display (LCD) device with reduced power consumption is provided with a plurality of data lines, a plurality of gate lines, and at least one demultiplexer. Each demultiplexer can comprise a plurality of switches respectively connected to the corresponding data lines and controlled by a plurality of clock signals and configured to receive an image signal, and selectively output the image signal to one of the data lines via the switches. During a driving period, one of the gate lines can be asserted, and the switches can be turned on simultaneously, then only the first one of the switches remains turned on to transmit the image signal to the corresponding data line, and then the first one of the switches are turned off and the other switches is sequentially turned on one at a time to transmit the image signal to the corresponding data lines.