Patents by Inventor Cheng-Lung Hung
Cheng-Lung Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11975421Abstract: The present disclosure provides a chemical mechanical polishing system having a unitary platen. The platen includes one or more recesses within the platen to house various components for the polishing/planarization process. In one embodiment, the platen includes a first recess and a second recess. The first recess is located under the second recess. An end point detector is placed in the first recess and a detector cover may be placed in the second recess. A sealing mean is provided in a space between the end point detector and the detector cover to prevent any external or foreign materials from coming in contact with the end point detector. A fastener used for fastening the detector cover to the platen also provides addition protection to prevent foreign materials from coming in contact with components received in the recesses.Type: GrantFiled: January 3, 2023Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Lung Lai, Cheng-Ping Chen, Shih-Chung Chen, Sheng-Tai Peng, Rong-Long Hung
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Publication number: 20240145543Abstract: A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yi LEE, Cheng-Lung HUNG, Chi On CHUI
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Patent number: 11955528Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate strip disposed over the substrate. The gate strip includes a high-k layer disposed over the substrate, an N-type work function metal layer disposed over the high-k layer, and a barrier layer disposed over the N-type work function metal layer. The barrier layer includes at least one first film containing TiAlN, TaAlN or AlN.Type: GrantFiled: October 11, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Weng Chang, Chi-On Chui
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Publication number: 20240113183Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.Type: ApplicationFiled: November 30, 2023Publication date: April 4, 2024Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Weng Chang, Chi On Chui
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Publication number: 20240103577Abstract: In one example, an electronic device may include a main body, and a back cover having an opening. The back cover may include an inner surface, and a hook protruding from the inner surface. The hook may be engageable with a receiving portion of the main body to slidably couple the back cover to the main body. Further, electronic device may include a component housing connected to the main body through the opening in the back cover to fixedly couple the back cover to the main body.Type: ApplicationFiled: November 5, 2019Publication date: March 28, 2024Applicant: Hewlett-Packard Development Company, L.P.Inventors: Cheng-Yi Yang, Szu Tao Tong, Hai-Lung Hung
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Patent number: 11935754Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nano structure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.Type: GrantFiled: June 30, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
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Patent number: 11935957Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: GrantFiled: August 9, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 11923240Abstract: A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate. The first transistor includes a first gate structure, and the second transistor includes a second gate structure. The first gate structure includes a first high-k layer, a first work function layer, an overlying work function layer, and a first capping layer sequentially formed on the substrate. The second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially formed on the substrate. The first capping layer and the second capping layer comprise materials having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.Type: GrantFiled: July 27, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Da-Yuan Lee
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Patent number: 11916114Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.Type: GrantFiled: June 30, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
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Publication number: 20240063061Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.Type: ApplicationFiled: November 1, 2023Publication date: February 22, 2024Inventors: Hsin-Han Tsai, Chung-Chiang Wu, Cheng-Lung Hung, Weng Chang, Chi On Chui
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Patent number: 11908893Abstract: A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.Type: GrantFiled: August 30, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
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Publication number: 20240021471Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.Type: ApplicationFiled: July 26, 2023Publication date: January 18, 2024Inventors: Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su
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Patent number: 11855163Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.Type: GrantFiled: June 23, 2020Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Weng Chang, Chi On Chui
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Patent number: 11855098Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.Type: GrantFiled: November 14, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
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Patent number: 11842928Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.Type: GrantFiled: June 30, 2022Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Han Tsai, Chung-Chiang Wu, Cheng-Lung Hung, Weng Chang, Chi On Chui
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Publication number: 20230387202Abstract: An embodiment includes a device having nanostructures on a substrate, the nanostructures including a channel region. The device also includes a gate dielectric layer wrapping around each of the nanostructures. The device also includes a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a first n-type work function metal, aluminum, and carbon, the first n-type work function metal having a work function value less than titanium. The device also includes a glue layer on the first work function tuning layer. The device also includes and a fill layer on the glue layer.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
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Patent number: 11810948Abstract: An embodiment includes a device having nanostructures on a substrate, the nanostructures including a channel region. The device also includes a gate dielectric layer wrapping around each of the nanostructures. The device also includes a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a first n-type work function metal, aluminum, and carbon, the first n-type work function metal having a work function value less than titanium. The device also includes a glue layer on the first work function tuning layer. The device also includes and a fill layer on the glue layer.Type: GrantFiled: May 11, 2021Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
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Publication number: 20230343834Abstract: Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.Type: ApplicationFiled: April 22, 2022Publication date: October 26, 2023Inventors: Hsin-Han TSAI, Hsiang-Ju LIAO, Yi-Lun LI, Cheng-Lung HUNG, Weng CHANG, Chi On CHUI, Jo-Chun HUNG, Chih-Wei LEE, Chia-Wei CHEN
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Publication number: 20230317446Abstract: The present disclosure describes a method for forming a semiconductor device having a work function metal layer doped with tantalum to mitigate oxygen diffusion and improve device threshold voltage. The method includes forming a gate dielectric layer on a channel structure and forming a work function metal layer on the gate dielectric layer. The gate dielectric layer includes an interfacial layer on the channel structure and a high-k dielectric layer on the interfacial layer. The method further includes doping the work function metal layer and the gate dielectric layer with tantalum.Type: ApplicationFiled: June 17, 2022Publication date: October 5, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yi LEE, Sheng-Yung Chang, Cheng-Lung Hung, Chi On Chui
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Patent number: 11769694Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.Type: GrantFiled: July 20, 2022Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su