Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Abstract: A display substrate and a display device, the display substrate includes a base substrate, a pixel driving circuit layer, a first planarization layer, a first metal layer, a second planarization layer, a plurality of first electrodes and a pixel definition layer; the pixel driving circuit layer includes a plurality of pixel driving circuits, the first planarization layer includes a plurality of first vias respectively exposing output terminals of the pixel driving circuits, the first metal layer includes a plurality of data lines extending in a first direction, the pixel definition layer includes a plurality of first definition walls extending in the first direction and a plurality of second definition walls extending in a second direction, and an orthographic projection of at least part of the data lines on the base substrate respectively overlaps with orthographic projections of the plurality of first definition walls on the base substrate.

Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels, the sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit is configured to drive the light-emitting element, and the light-emitting element includes a first electrode, a second electrode, and a light-emitting functional layer located therebetween; the pixel circuit includes a driving transistor, and the first electrode of the light-emitting element is electrically connected to a first electrode of the driving transistor; the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel is adjacent to the second sub-pixel, and an orthographic projection of the first electrode of the light-emitting element of the first sub-pixel on the base substrate does not overlap an orthographic projection of the pixel circuit of the second sub-pixel on the base substrate.

Abstract: Embodiments of the present disclosure provide a drive apparatus and a display apparatus. The drive apparatus includes: a first controller configured to generate and output a data control synchronization signal after being energized, the data control synchronization signal is configured to control whether to load a data voltage onto a data line in a touch display panel to be connected; and a second controller connected with the first controller, and configured to directly output a first set level signal and a second set level signal before being energized; where the first set level signal is configured to control the selection of a display drive mode from a plurality of drive modes supported by the touch display panel to be connected; and the second set level signal is configured to control the output of a drive signal corresponding to the display drive mode to the touch display panel to be connected.

Abstract: Provided are a transformer winding and a method for constructing a transformer winding. The transformer winding includes: a lead wire of a winding conductor of the transformer winding; an insulating layer wrapping the lead wire; a ground shielding layer covering a side, close to the winding conductor, of the insulating layer; and a stress grading material layer, which is made of a semi-conductive material, covers a side, away from the winding conductor, of the insulating layer, and is electrically connected to the ground shielding layer, where the stress grading material layer is impedance-matched with the insulating layer.

Abstract: Provided is a recognition method of 3D vein pattern including the following steps. A plurality of first light beams are emitted by a recognition device to a wrist of a user. A plurality of first reflected light beams from the wrist are received by the recognition device to form a first 3D vein pattern of the wrist. Differences between the first 3D vein pattern and a wrist vein pattern of a database are compared to identify an identity or a gesture of the user. A recognition device of 3D vein pattern is also provided.

Abstract: A grid-driving-circuit array is applied to a display panel, the display panel is delimited into a plurality of active areas, and each of the active areas includes multiple rows of pixel units and multiple rows of grid lines. The multiple groups of grid driving units supply grid driving signals to the plurality of active areas, and each of the groups of grid driving units includes one or more grid driving circuits. The one or more grid driving circuits are configured for supplying the grid driving signals to the grid lines within the active area corresponding to the one or more grid driving circuits. One or more multiplexers, wherein each of the multiplexers includes a plurality of frame-starting-up-signal outputting units, each of the frame-starting-up-signal outputting units of the multiplexer is configured for supplying a frame starting-up signal to one of the grid driving circuits.

Abstract: Pixel circuit, driving method, display substrate, panel and device are disclosed. The pixel circuit includes light-emitting element, and pixel driving circuit including driving circuit, data writing circuit and compensation control circuit; the data writing circuit writes data voltage into control end of driving circuit under control of write control signal in data writing phase; the compensation control circuit writes reference voltage into the control end of driving circuit under control of compensation control signal in compensation phase; the driving circuit is electrically connected to the light-emitting element, and is configured to drive the light-emitting element; the data writing phase does not overlap with the compensation phase.

Abstract: Provided are a transformer winding and a method for constructing a transformer winding. The transformer winding includes: a winding conductor having a ring structure; a first insulating layer wrapped on a surface of the winding conductor formed by winding; a conductor tape attached in an unclosed surrounding manner to a surface of the first insulating layer along a circumferential direction of the first insulating layer, where the conductor tape is attached to a position having a minimum value of a leakage flux on the surface of the first insulating layer; a first shielding layer attached to the surface of the first insulating layer with the conductor tape attached thereto; a second insulating layer cast outside the first shielding layer; and a second shielding layer wrapped on an outer surface of the second insulating layer.

Abstract: A harmonic suppression method and apparatus for a three-phase three-wire cascaded power conversion apparatus is disclosed.

Abstract: Provided is a direct current voltage sampling circuit used for a medium-voltage power module. The medium-voltage power module includes two cascaded H-bridge circuits. The sampling circuit includes two sampling sub-circuits, with each connected to one H-bridge circuit. The sampling sub-circuit includes: a voltage dividing circuit connected in parallel to an output end of the H-bridge circuit, an isolation module connected to the voltage dividing circuit, a direct current isolated power supply which supplies power to the isolation module independently of the H-bridge circuit, and an amplifier conditioning module which converts an isolated voltage signal into a sampled voltage output. Parasitic capacitances of the isolation module and the direct current isolated power supply are both less than 2 pF, and the sampled voltage outputs of the two sampling sub-circuits are provided to a same local controller.

Abstract: A method of complementing a map of a scene with 3D reference points including four steps. In a first step, data is collected and recorded based on samples of at least one of an optical sensor, a GNSS, and an IMU. A second step includes initial pose generation by processing of the collected sensor data to provide a track of vehicle poses. A pose is based on a specific data set, on at least one data set recoded before that dataset and on at least one data set recorded after that data set. A third step includes SLAM processing of the initial poses and collected optical sensor data to generate keyframes with feature points. In a fourth step 3D reference points are generated by fusion and optimization of the feature points by using future and past feature points together with a feature point at a point of processing. This second and fourth steps provides significantly better results than SLAM or VIO methods known from prior art, as the second and the fourth steps are based on recorded data.

Abstract: The present application relates to a silicone oil-based immersion coolant for an electronic component. The silicone oil-based immersion coolant for an electronic component includes a base oil and an additive. The base oil includes a low-viscosity silicone oil. The additive includes a silicone oil diluent and a thermally conductive inorganic filler. The viscosity of the low-viscosity silicone oil is less than or equal to 1000 cSt. The thermally conductive inorganic filler is an insulating filler. Based on the mass of the immersion coolant, a mass percentage content of the base oil is in a range from 70% to 85%, a mass percentage content of the silicone oil diluent is in a range from 10% to 20%, and a mass percentage content of the thermally conductive inorganic filler is in a range from 5% to 10%.

Abstract: The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.

Abstract: Methods, systems, and devices for skipping pages for weak wordlines of a memory device during pre-programming are described. A memory device may be configured to operate in a first mode involving skipping one or more pages (e.g., a lower page (LP)) associated with a set of wordlines. In some examples, a testing system may determine the set of wordlines (e.g., weak wordlines) for which to skip pages according to performance degradation for the wordlines in response to applying a threshold temperature to a test memory device. In the first mode, the memory device may store (e.g., pre-program) data in a subset of pages distinct from the skipped pages. The memory device may switch to a second mode in response to a trigger condition. In the second mode, the memory device may use each page associated with the wordlines and may refrain from skipping the one or more pages.

Abstract: Disclosed herein is an instrument and associated methods for a fully automated bench-top NULISA platform, comprising an X-Y-Z-gantry, a microtiter plate stage, an incubator, a quantitative PCR module, a decontamination cleaner for microtiter plates, a microtiter plate sealer, a magnetic probe and comb assembly for sample mixing and magnetic bead extraction, a storage unit for reagents and supplies, and a controller.

Abstract: A display panel includes a plurality of rows of pixel circuits, one or more rows of first dummy pixel circuits, a plurality of cascaded scanning driving units and at least one first dummy scanning driving unit. The plurality of rows of pixel circuits are arranged in a first direction. The one or more rows of first dummy pixel circuits are located on a side of the plurality of rows of pixel circuits in the first direction. Each scanning driving unit is configured to transmit a scanning signal to at least one row of pixel circuits. A first dummy scanning driving unit is cascaded to a first stage of scanning driving unit among the plurality of scanning driving units, and is configured to transmit; a cascade signal to the first stage of scanning driving unit; and transmit scanning signals to at least one row of first dummy pixel circuits.

Abstract: A driving circuit, a driving method and a display device are provided. The driving circuit includes a first control node control circuit, a second control node control circuit, a first node control circuit and a second node control circuit, wherein, the first control node control circuit is configured to control a potential of the first control node; the second control node control circuit is configured to control a potential of the second control node; the first node control circuit is configured to control a potential of the first node; the second node control circuit is electrically connected to the second control node, a first clock signal terminal and a second node respectively, and is configured to control to connect the first clock signal terminal and the second node under the control of the potential of the second control node.

Abstract: A display substrate and a display device, the display substrate includes a base substrate, a pixel driving circuit layer, a first planarization layer, a first metal layer, a second planarization layer, a plurality of first electrodes and a pixel definition layer; the pixel driving circuit layer includes a plurality of pixel driving circuits, the first planarization layer includes a plurality of first vias respectively exposing output terminals of the pixel driving circuits, the first metal layer includes a plurality of data lines extending in a first direction, the pixel definition layer includes a plurality of first definition walls extending in the first direction and a plurality of second definition walls extending in a second direction, and an orthographic projection of at least part of the data lines on the base substrate respectively overlaps with orthographic projections of the plurality of first definition walls on the base substrate.