Abstract: A semiconductor device having a low-k isolation structure and a method for forming the same are provided. The semiconductor device includes channel structures, laterally extending on a substrate; gate structures, intersecting and covering the channel structures; and a channel isolation structure, laterally penetrating through at least one of the channel structures, and extending between separate sections of one of the gate structures along an extending direction of the one of the gate structures. A low-k dielectric material in the channel isolation structure comprises boron nitride.

Abstract: The present disclosure discloses a color temperature control circuit, including a signal input circuit, a main control chip U1, and a color temperature adjustment circuit. The color temperature adjustment circuit includes an optocoupler OP1, a first adjustment circuit, and a second adjustment circuit. The first adjustment circuit includes a field-effect transistor Q1 and a first light-emitting bead group; the second adjustment circuit includes a field-effect transistor Q2 and a second light-emitting bead group; color temperatures of the first and second light-emitting bead groups are different, a drain electrode of the field-effect transistor Q1 is connected to a grid electrode of the field-effect transistor Q2 through a diode D2. The main control chip U1 recognizes an input control signal, then outputs a signal to the optocoupler OP1, and controls a conduction of the field-effect transistors Q1 and Q2 through a high level and a low level, respectively.

Abstract: A method includes: performing a first inspection on a reticle in a reticle pod, the reticle pod including a sealed space to accommodate the reticle, and the reticle pod further comprising an inspection window, wherein the first inspection is performed through the inspection window with the sealed space keeping sealed; and moving the reticle out of the reticle pod for performing a first operation of a semiconductor device using the reticle in response to determining no defect found on the reticle.

Abstract: Some implementations described herein provide pixel sensor configurations and methods of forming the same. In some implementations, one or more transistors of a pixel sensor are included on a circuitry die (e.g., an application specific integrated circuit (ASIC) die or another type of circuitry die) of an image sensor device. The one or more transistors may include a source follower transistor, a row select transistor, and/or another transistor that is used to control the operation of the pixel sensor. Including the one or more transistors of the pixel sensor (and other pixel sensors of the image sensor device) on the circuitry die reduces the area occupied by transistors in the pixel sensor on the sensor die. This enables the area for photon collection in the pixel sensor to be increased.

Abstract: A smart dialing recommendation method, a non-transitory computer-readable medium, and a mobile device are disclosed. The smart dialing recommendation method includes: establishing a database according to a correspondence between a plurality of different time intervals in a past time range and a plurality of communication numbers by using a machine learning algorithm; obtaining a time stamp; and determining whether the time stamp has expired. When it is determined that the time stamp has not expired, according to the correspondence in the database and a current time point, a recommended number corresponding to the current time point is retrieved from the plurality of communication numbers. When it is determined that the time stamp has expired, the machine learning algorithm is performed again to update the plurality of communication numbers.

Abstract: The present disclosure provides a method that includes providing a semiconductor structure having a bottom channel region and a top channel region over the bottom channel region; forming a gate dielectric layer over and wrapping around top channels in the top channel region; performing a radical treatment on the dielectric layer in a supercritical fluid; and forming a metal gate electrode on the dielectric layer.

Abstract: The present disclosure provides a method that includes providing a semiconductor structure having a bottom channel region and a top channel region over the bottom channel region; forming a gate dielectric layer over and wrapping around top channels in the top channel region; performing a radical treatment on the dielectric layer in a supercritical fluid; and forming a metal gate electrode on the dielectric layer.

Abstract: A method includes forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A first dipole film and a second dipole film are formed on the first gate dielectric and the second gate dielectric, respectively. The Dipole dopants in the first dipole film and the second dipole film are driven into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are then removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form first transistor and a second transistor, respectively.

Abstract: A thermoelectric cooler (TEC) is positioned to move heat away from a hot spot on a semiconductor chip and toward a dielectric substrate. This approach to thermal management is particularly effective when used in conjunction with a buried rail and back side power delivery. The TEC may be in a layer that contains solder connections be between two device layers an IC package. Alternatively, the TEC may be in a metal interconnect structure over the semiconductor substrate such as in a passivation stack at the top of the metal interconnect structure. TECs at either of these locations may be formed by wafer-level processing.

Abstract: A method includes forming a semiconductor fin; forming a gate dielectric layer over the semiconductor fin; depositing a first work function metal layer over the gate dielectric layer, the first work function metal layer having a first concentration of a work function material; depositing a second work function metal layer over the first work function metal layer, the second work function metal layer having a second concentration of the work function material, wherein the first concentration is higher than the second concentration; and forming a gate electrode over the second work function metal layer.

Abstract: A method for cleaning is provided. The method includes: removing a pellicle frame from a top surface of a photomask by debonding an adhesive between the photomask and the pellicle frame, wherein a first portion of the adhesive is remained on the top surface of the photomask, and removing the first portion of the adhesive on the top surface of the photomask, including applying an alkaline solution to the top surface of the photomask, and performing a mechanical impact to the photomask.

Abstract: An image sensing apparatus is disclosed. The image sensing apparatus includes a pixel array and micro lenses disposed above the pixel array. The pixel array includes sensing pixels configured to capture minutia points of a fingerprint and positioning pixels configured to provide positioning codes.

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

Abstract: A semiconductor device includes a first type of light sensing units, where each instance of the first type of light sensing units is operable to receive a first amount of radiation; and a second type of light sensing units, where each instance of the second type of light sensing units is operable to receive a second amount of radiation, and the second type of light sensing units is arranged in an array with the first type of light sensing units to form a pixel sensor. The first amount of radiation is smaller than the second amount of radiation, and at least a first instance of the first type of light sensing units is adjacent to a second instance first type of light sensing unit.

Abstract: In one example in accordance with the present disclosure, an example computing device is disclosed. The example computing device includes a housing. The example computing device also includes a rotatable antenna disposed within the housing. The rotatable antenna is to rotate such that a direction of radiation is maintained in a single direction as the housing is to rotate.

Abstract: A method includes: inspecting a reticle in a reticle pod, the reticle pod including a sealed space to accommodate the reticle, and the reticle pod further comprising a window arranged on an upper surface of the reticle pod, wherein the inspecting is performed through the window; and moving the reticle out of the reticle pod for performing a lithography operation using the reticle.

Abstract: Some implementations described herein provide pixel sensor configurations and methods of forming the same. In some implementations, one or more transistors of a pixel sensor are included on a circuitry die (e.g., an application specific integrated circuit (ASIC) die or another type of circuitry die) of an image sensor device. The one or more transistors may include a source follower transistor, a row select transistor, and/or another transistor that is used to control the operation of the pixel sensor. Including the one or more transistors of the pixel sensor (and other pixel sensors of the image sensor device) on the circuitry die reduces the area occupied by transistors in the pixel sensor on the sensor die. This enables the area for photon collection in the pixel sensor to be increased.

Abstract: A pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (NIR) pixel sensors. The color information obtained by the visible light pixel sensors and the luminance obtained by the NIR pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. The capability to accommodate different sizes of visible light pixel sensors and NIR pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.

Abstract: The invention discloses a superconductor-metal conductive material, comprising a metal powder, a superconductor powder and an organic carrier adhesive, wherein the metal powder has 50-95 wt % of a total weight of said metal powder, said superconductor powder and said organic carrier binder, the superconductor powder has 4-40 wt % of said total weight, and the organic carrier binder has 1-10 wt % of said total weight, wherein the superconductor powder comprises one or more mixtures of La2-x-ySrxBayCuO4, La2-x-y BixSryCuO4, La2-x-y-z BixSryCaZCuO4, La2-x-y-z HgxBayCazCuO4, La2-x-ySrxTlyBazCuO6, La2-x-y-z-wSrxTlyBazCawCu2O8, and HgBa2Ca2Cu3O8, where each of x, y, z, and w is between 0.1 and 0.9.

Abstract: A silicon interconnect die includes through-substrate via (TSV) structures extending through a silicon substrate; an insulating spacer layer including a horizontally-extending portion overlying a top surface of the silicon substrate and a plurality of tubular insulating material portions laterally surrounding a respective one of the TSV structures; and a front metallic shield layer including a horizontally-extending metallic shield portion and at least one tubular metallic shield portion laterally surrounding a respective one of the tubular insulating material portions.