Abstract: A semiconductor device includes a first type of light sensing units, where each instance of the first type of light sensing units is operable to receive a first amount of radiation; and a second type of light sensing units, where each instance of the second type of light sensing units is operable to receive a second amount of radiation, and the second type of light sensing units is arranged in an array with the first type of light sensing units to form a pixel sensor. The first amount of radiation is smaller than the second amount of radiation, and at least a first instance of the first type of light sensing units is adjacent to a second instance first type of light sensing unit.

Abstract: In one example in accordance with the present disclosure, an example computing device is disclosed. The example computing device includes a housing. The example computing device also includes a rotatable antenna disposed within the housing. The rotatable antenna is to rotate such that a direction of radiation is maintained in a single direction as the housing is to rotate.

Abstract: A method includes: inspecting a reticle in a reticle pod, the reticle pod including a sealed space to accommodate the reticle, and the reticle pod further comprising a window arranged on an upper surface of the reticle pod, wherein the inspecting is performed through the window; and moving the reticle out of the reticle pod for performing a lithography operation using the reticle.

Abstract: Some implementations described herein provide pixel sensor configurations and methods of forming the same. In some implementations, one or more transistors of a pixel sensor are included on a circuitry die (e.g., an application specific integrated circuit (ASIC) die or another type of circuitry die) of an image sensor device. The one or more transistors may include a source follower transistor, a row select transistor, and/or another transistor that is used to control the operation of the pixel sensor. Including the one or more transistors of the pixel sensor (and other pixel sensors of the image sensor device) on the circuitry die reduces the area occupied by transistors in the pixel sensor on the sensor die. This enables the area for photon collection in the pixel sensor to be increased.

Abstract: A pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (NIR) pixel sensors. The color information obtained by the visible light pixel sensors and the luminance obtained by the NIR pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. The capability to accommodate different sizes of visible light pixel sensors and NIR pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.

Abstract: The invention discloses a superconductor-metal conductive material, comprising a metal powder, a superconductor powder and an organic carrier adhesive, wherein the metal powder has 50-95 wt % of a total weight of said metal powder, said superconductor powder and said organic carrier binder, the superconductor powder has 4-40 wt % of said total weight, and the organic carrier binder has 1-10 wt % of said total weight, wherein the superconductor powder comprises one or more mixtures of La2-x-ySrxBayCuO4, La2-x-y BixSryCuO4, La2-x-y-z BixSryCaZCuO4, La2-x-y-z HgxBayCazCuO4, La2-x-ySrxTlyBazCuO6, La2-x-y-z-wSrxTlyBazCawCu2O8, and HgBa2Ca2Cu3O8, where each of x, y, z, and w is between 0.1 and 0.9.

Abstract: A silicon interconnect die includes through-substrate via (TSV) structures extending through a silicon substrate; an insulating spacer layer including a horizontally-extending portion overlying a top surface of the silicon substrate and a plurality of tubular insulating material portions laterally surrounding a respective one of the TSV structures; and a front metallic shield layer including a horizontally-extending metallic shield portion and at least one tubular metallic shield portion laterally surrounding a respective one of the tubular insulating material portions.

Abstract: The present disclosure provides a method that includes providing a semiconductor structure having a bottom channel region and a top channel region over the bottom channel region; forming a gate dielectric layer over and wrapping around top channels in the top channel region; performing a radical treatment on the dielectric layer in a supercritical fluid; and forming a metal gate electrode on the dielectric layer.

Abstract: An application of a cloud-based controller forwards a message to a message broker of the cloud-based controller. The message is then transmitted to a network device of a wireless communications network over a persistent hypertext transfer protocol (“HTTP”) connection. Thereafter, an acknowledgment is received in response to transmitting the message at a gRPC proxy for the message broker.

Abstract: A computer system is described. This computer system may implement a controller for multiple different types of computer network devices (CNDs), such as: an access point, a switch, a router, and a dataplane. Moreover, the computer system may have a common framework for program modules (with sets of program instructions) associated with the different types of CNDs. Furthermore, configuration and management of a given type of CND using the program modules may be specified by metadata associated with the given type of CND. Additionally, the common framework may include a unified protocol layer for the program modules, and one or more of the program modules may be modified or configured via the unified protocol layer using a common communication Alternatively or additionally, the computer system may communicate with the different types of CNDs via the unified protocol layer using a second common communication protocol.

Abstract: A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurali

Abstract: An image sensor device and methods of forming the same are described. In some embodiments, the device includes a substrate, a contact pad structure extending from a contact pad region to a black level correction region, a dielectric layer disposed over the substrate in the black level correction region, and a light blocking structure disposed on and through the dielectric layer in the black level correction region. A first portion of the contact pad structure disposed in the black level correction region is in contact with the light blocking structure, and the light blocking structure is in contact with the substrate.

Abstract: A pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (NIR) pixel sensors. The color information obtained by the visible light pixel sensors and the luminance obtained by the NIR pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. The capability to accommodate different sizes of visible light pixel sensors and NIR pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.

Abstract: A pixel array may include a group of time-of-flight (ToF) sensors. The pixel array may include an image sensor comprising a group of pixel sensors. The image sensor may be arranged among the group of ToF sensors such that the image sensor is adjacent to each ToF sensor in the group of ToF sensors.

Abstract: An optical blocking region formed with patterned metal reduces light reflection toward pixel sensors in a pixel sensor array. The optical blocking region may be formed of a metal nanoscale grid in order to reflect more light away from the pixel sensors. The optical blocking region may include a dielectric layer, supporting the patterned metal, with high absorption structures or shallow deep trench isolation structures in order to increase absorption and thus reduce light reflection toward the pixel sensors.

Abstract: In-pixel separation structures may divide photodiodes of a pixel array into multiple regions. As a result, a lens of an image sensor device may be focused by using combining signals associated with different portions of the photodiodes. As a result, the lens may be focused faster and with fewer pixels of the pixel array, which conserves power, processing resources, and raw materials.

Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.

Abstract: A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate dielectric layer is formed to wrap around semiconductor fin. A P-type work function layer is formed to wrap around the gate dielectric layer. An N-type work function layer is formed to wrap around the P-type work function layer. The N-type work function layer has a work function different from a work function of the P-type work function layer. The N-type work function layer is treated such that an upper portion of the N-type work function layer has a different composition than a lower portion of the N-type work function layer.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of finFETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first dielectric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.