Patents by Inventor Cheng-Ming Yih
Cheng-Ming Yih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150194314Abstract: A method of fabricating a semiconductor device is provided. A substrate having a first region and a second region is provided. A plurality of stacked gate structures are formed on the substrate of the first region. Each stacked gate structure includes a tunneling dielectric layer, a charge storage layer, an inter-gate dielectric layer, and a control gate. A gap exists between two adjacent stacked gate structures. At least one gate structure is formed on the substrate of the second region. A liner layer is conformally formed on the substrate. A dielectric layer covering the liner layer is formed in the second region. A metal silicide layer is formed on the top portion of the gate structure and on the substrate on both sides of the gate structure. A contact process is performed to form a plurality of contacts connected to the metal silicide layer.Type: ApplicationFiled: May 15, 2014Publication date: July 9, 2015Applicant: MACRONIX International Co., Ltd.Inventors: Ta-Kang Chu, Hung-Chi Chen, Cheng-Ming Yih
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Patent number: 8547755Abstract: Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.Type: GrantFiled: December 7, 2012Date of Patent: October 1, 2013Assignee: Macronix International Co., Ltd.Inventors: Yi-Fan Chang, Cheng Ming Yih, Su-chueh Lo, Jian Shing Liu, Kuen Long Chang, Chun-Hsiung Hung
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Patent number: 8471324Abstract: A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates.Type: GrantFiled: September 15, 2009Date of Patent: June 25, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Tin-Wei Wu, Cheng-Ming Yih, Chih-Hsiang Yang
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Patent number: 8451641Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.Type: GrantFiled: July 13, 2012Date of Patent: May 28, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Publication number: 20130100745Abstract: Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.Type: ApplicationFiled: December 7, 2012Publication date: April 25, 2013Inventors: Yi-Fan Chang, Cheng Ming Yih, Su-chueh Lo, Jian Shing Liu, Kuen Long Chang, Chun-Hsiung Hung
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Patent number: 8339861Abstract: Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.Type: GrantFiled: July 12, 2010Date of Patent: December 25, 2012Assignee: Macronix International Co., Ltd.Inventors: Yi-Fan Chang, Cheng Ming Yih, Su-chueh Lo, Jian Shing Liu, Kuen-Long Chang, Chun-Hsiung Hung
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Publication number: 20120300553Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.Type: ApplicationFiled: August 6, 2012Publication date: November 29, 2012Applicant: Macronix International Co., Ltd.Inventors: Yi-Fan Chang, Su-chueh Lo, Cheng Ming Yih, Ta Kang Chu, Chu Ching Wu, Kuo Yu Liao, Ken Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
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Publication number: 20120273842Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.Type: ApplicationFiled: July 13, 2012Publication date: November 1, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Patent number: 8259499Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.Type: GrantFiled: June 29, 2010Date of Patent: September 4, 2012Assignee: Macronix International Co., Ltd.Inventors: Yi-Fan Chang, Su-chueh Lo, Cheng Ming Yih, Ta Kang Chu, Chu Ching Wu, Kuo Yu Liao, Ken Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: 8243489Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.Type: GrantFiled: March 10, 2011Date of Patent: August 14, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Patent number: 8097912Abstract: A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.Type: GrantFiled: June 13, 2007Date of Patent: January 17, 2012Assignee: Macronix International Co. Ltd.Inventors: Cheng-Ming Yih, Chu-Ching Wu, Huei-Huarng Chen
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Publication number: 20110317493Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.Type: ApplicationFiled: June 29, 2010Publication date: December 29, 2011Applicant: Macronix International Co., Ltd.Inventors: Yi-Fan Chang, Su-chueh Lo, Cheng Ming Yih, Ta Kang Chu, Chu Ching Wu, Kuo Yu Liao, Ken Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: 8043908Abstract: A method of fabricating a semiconductor device is provided. First, a stacked structure is formed on a substrate. The stacked structure includes, from the substrate, a dielectric layer and a conductive gate in order. An ion implant process is performed to form doped regions in the substrate on the opposite sides of the stacked structure. Thereafter, source-side spacer is formed on a sidewall of the stacked structure. A thermal process is performed to activate the doped regions, thereby forming a source in the substrate under the sidewall of the stacked structure having the source-side spacer and a drain in the substrate on another side of the stacked structure.Type: GrantFiled: August 6, 2010Date of Patent: October 25, 2011Assignee: MACRONIX International Co., Ltd.Inventor: Cheng-Ming Yih
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Publication number: 20110156102Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.Type: ApplicationFiled: March 10, 2011Publication date: June 30, 2011Applicant: MACRONIX International Co., Ltd.Inventors: CHUN-YUAN LO, Cheng-Ming Yih, Wen-Pin Lu
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Publication number: 20110128791Abstract: Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.Type: ApplicationFiled: July 12, 2010Publication date: June 2, 2011Applicant: Macronix International Co., Ltd.Inventors: Yi-Fan Chang, Cheng Ming Yih, Su-chueh Lo, Jian Shing Liu, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: 7924591Abstract: A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.Type: GrantFiled: February 6, 2009Date of Patent: April 12, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Publication number: 20110062507Abstract: A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates.Type: ApplicationFiled: September 15, 2009Publication date: March 17, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Tin-Wei Wu, Cheng-Ming Yih, Chih-Hsiang Yang
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Publication number: 20100323483Abstract: A method of fabricating a semiconductor device is provided. First, a stacked structure is formed on a substrate. The stacked structure includes, from the substrate, a dielectric layer and a conductive gate in order. An ion implant process is performed to form doped regions in the substrate on the opposite sides of the stacked structure. Thereafter, source-side spacer is formed on a sidewall of the stacked structure. A thermal process is performed to activate the doped regions, thereby forming a source in the substrate under the sidewall of the stacked structure having the source-side spacer and a drain in the substrate on another side of the stacked structure.Type: ApplicationFiled: August 6, 2010Publication date: December 23, 2010Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventor: Cheng-Ming Yih
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Patent number: 7846794Abstract: flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.Type: GrantFiled: November 21, 2007Date of Patent: December 7, 2010Assignee: Macronix International Co., Ltd.Inventors: Chu-Ching Wu, Cheng-Ming Yih
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Patent number: 7795665Abstract: A flash memory comprising a substrate, a stacked structure over the substrate, a source, a drain and a source-side spacer is provided. The stacked structure includes a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The source and the drain are disposed in the substrate on the sides of the floating gate, respectively. The source-side spacer is disposed on a sidewall of the stacked structure near the source, thereby preventing the tunneling oxide layer and the inter-gate dielectric layer near the source from being re-oxidized, resulting in an increased thickness.Type: GrantFiled: June 22, 2007Date of Patent: September 14, 2010Assignee: MACRONIX International Co., Ltd.Inventor: Cheng-Ming Yih