Abstract: A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.

Abstract: A memory and a method of fabricating the same are provided. The memory is disposed on a substrate in which a plurality of trenches is arranged in parallel. The memory includes a gate structure and a doped region. The gate structure is disposed between the trenches. The doped region is disposed at one side of the gate structure, in the substrate between the trenches and in the sidewalls and bottoms of the trenches. The top surface of the doped region in the substrate between the trenches is lower than the surface of the substrate under the gate structure by a distance, and the distance is greater than 300 ?.

Abstract: A memory and a method of fabricating the same are provided. The memory is disposed on a substrate in which a plurality of trenches is arranged in parallel. The memory includes a gate structure and a doped region. The gate structure is disposed between the trenches. The doped region is disposed at one side of the gate structure, in the substrate between the trenches and in the sidewalls and bottoms of the trenches. The top surface of the doped region in the substrate between the trenches is lower than the surface of the substrate under the gate structure by a distance, and the distance is greater than 300 ?.

Abstract: A data writing method for flash memories suitable for a flash memory using a switching unit to control a bit line thereof is disclosed. The data writing method for flash memories includes applying a square wave signal to a word line of the flash memory and applying a descent wave signal to the switching unit for the bit line of the flash memory to receive a fixed drain voltage.

Abstract: A data writing method for flash memories suitable for a flash memory using a switching unit to control a bit line thereof is disclosed. The data writing method for flash memories includes applying a square wave signal to a word line of the flash memory and applying a descent wave signal to the switching unit for the bit line of the flash memory to receive a fixed drain voltage.

Abstract: A flash memory comprising a substrate, a stacked structure over the substrate, a source, a drain and a source-side spacer is provided. The stacked structure includes a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The source and the drain are disposed in the substrate on the sides of the floating gate, respectively. The source-side spacer is disposed on a sidewall of the stacked structure near the source, thereby preventing the tunneling oxide layer and the inter-gate dielectric layer near the source from being re-oxidized, resulting in an increased thickness.

Abstract: A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.

Abstract: A method for forming a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate, having a trench-like opening therein exposing a portion of the substrate. A thermal oxidation process is performed to the substrate. An anisotropic etching process is performed using the patterned mask layer as a mask to form a trench in the substrate, and then the trench is filled with an insulating material.

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract: A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract: A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.

Abstract: A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract: A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.

Abstract: A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.

Abstract: A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.

Abstract: A corner free structure of a nonvolatile memory is disclosed in this present invention. The key aspect of this present invention is employing a corner free structure for isolating a trench isolation device and a nonvolatile memory, and thus the reliability of the above-mentioned nonvolatile memory is improved. Furthermore, based on the definition of coupling ratio, as a result of the above-cited corner free structure, the effective channel area of the nonvolatile memory is modified, and thus the nonvolatile memory according to this present invention can achieve higher efficiency than the nonvolatile memory in the prior art. Therefore, this invention can not only improve the reliability of a nonvolatile memory, but also advance the efficiency of the nonvolatile memory.