Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: A manufacturing method of housing structure of electronic device is provided. The manufacturing method includes stacking a first structural layer, a painting layer, and a second structural layer, wherein the painting layer is located between the first and the second structural layers. The layer stacked after the painting layer washes and squeezes at least a portion of the flowing painting layer to form a random texture pattern.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A physiological detection device includes system including a first array PPG detector, a second array PPG detector, a display and a processing unit. The first array PPG detector is configured to generate a plurality of first PPG signals. The second array PPG detector is configured to generate a plurality of second PPG signals. The display is configured to show a detected result of the physiological detection system. The processing unit is configured to convert the plurality of first PPG signals and the plurality of second PPG signals to a first 3D energy distribution and a second 3D energy distribution, respectively, and control the display to show an alert message.

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

Abstract: A casing structure of electronic device including a metal base plate, a transparent cathodic electrodeposition paints layer, and a transparent paints coating layer is provided. The metal base plate has brushed texture and high gloss surface. The transparent cathodic electrodeposition paints layer is disposed on the base metal base plate. The transparent paints coating layer is disposed on the transparent cathodic electrodeposition paints layer. A manufacturing method of casing structure of electronic device is also provided.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: In a method of forming a heat dissipating structure for a semiconductor chip, a soldering material is disposed on a top surface of the semiconductor chip. A first region of metal plating is formed on a surface of a lid. The first region has a first width and a first length. The first width is larger than a second width of the top surface of the semiconductor chip and the first length is larger than a second length of the top surface of the semiconductor chip. The lid is placed over the semiconductor chip so that the first region of metal plating of the lid is disposed over the soldering material to bond the lid to the semiconductor chip by a soldering material layer having an inverted trapezoidal shape between the lid and the top surface of the semiconductor chip.

Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

Abstract: A semiconductor device package is disclosed. The semiconductor device package includes a carrier, a first electronic component disposed on the carrier and a support component disposed on the carrier. The semiconductor device package also includes a second electronic component disposed on the first electronic component and supported by the support component.

Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first heat conductive layer between the heat-spreading wall structure and the chip. The chip package structure includes a second heat conductive layer over the chip and surrounded by the first heat conductive layer. The chip package structure includes a heat-spreading lid over the substrate and covering the heat-spreading wall structure, the first heat conductive layer, the second heat conductive layer, and the chip. The heat-spreading lid is bonded to the substrate, the heat-spreading wall structure, the first heat conductive layer, and the second heat conductive layer.

Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a substrate. The method includes forming a heat-spreading wall structure over the substrate. The heat-spreading wall structure is adjacent to the chip, and there is a first gap between the chip and the heat-spreading wall structure. The method includes forming a first heat conductive layer in the first gap. The method includes forming a second heat conductive layer over the chip. The method includes disposing a heat-spreading lid over the substrate to cover the heat-spreading wall structure, the first heat conductive layer, the second heat conductive layer, and the chip. The heat-spreading lid is bonded to the substrate, the heat-spreading wall structure, the first heat conductive layer, and the second heat conductive layer.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first electronic component having an active surface and a backside surface opposite to the active surface and a first antenna layer disposed on the backside surface of the first electronic component. The semiconductor device package further includes a first dielectric layer covering the first antenna layer and a second antenna layer disposed over the first antenna layer. The second antenna layer is spaced apart from the first antenna layer by the first dielectric layer. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: A semiconductor device package includes a substrate, a first molding compound and antenna layer. The substrate has a first surface and a second surface opposite to the first surface. The first molding compound is disposed on the first surface of the substrate. The antenna layer is disposed on the first molding compound. The substrate, the first molding compound and the antenna layer define a cavity.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first electronic component having an active surface and a backside surface opposite to the active surface and a first antenna layer disposed on the backside surface of the first electronic component. The semiconductor device package further includes a first dielectric layer covering the first antenna layer and a second antenna layer disposed over the first antenna layer. The second antenna layer is spaced apart from the first antenna layer by the first dielectric layer. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: An OLED touch display operation method is disclosed. The OLED touch display operation method includes the following steps: controlling a touch scan transition timing and a display multiplexer switching timing to maintain a specific equidistant relationship; when the OLED touch display performs display function, the OLED touch display performs touch scanning only for a part of display time, and stops touch scanning or performs touch voltage compensation scanning for another part of display time; and when being interfered by external noise, the OLED touch display performs touch scanning only in a blanking period out of the display time and the touch scanning frequency can be adjusted to avoid interference of external noise.

Abstract: An electronic device package includes a first conductive substrate, a second conductive substrate and a dielectric layer. The first conductive substrate has a first coefficient of thermal expansion (CTE). The second conductive substrate is disposed on an upper surface of the first conductive substrate and electrically connected to the first conductive substrate. The second conductive substrate has a second CTE. The dielectric layer is disposed on the upper surface of the first conductive substrate and disposed on at least one sidewall of the second conductive substrate. The dielectric layer has a third CTE. A difference between the first CTE and the second CTE is larger than a difference between the first CTE and the third CTE.

Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.