Abstract: The present application provides a tunable phase shifter and an electronic device, which relates to the technical field of microwave radio frequency. The tunable phase shifter includes: a first substrate and a second substrate; and a regulatable dielectric layer. The first electrode layer includes a reference electrode. The second electrode layer includes a first transmission line and a second transmission line, the first transmission line is provided with a first branch, the second transmission line is provided with a second branch, and the orthographic projections on the first substrate of the first branch and the second branch and the orthographic projection of the reference electrode on the first substrate at least partially overlap. The tunable phase shifter according to the present application forms an electric field by using the first branch, the second branch and the reference electrode, which can realize the function of phase shifting.

Abstract: Various embodiments of the teachings herein include a method for measuring valve characteristic parameters of a valve actuator. An example method includes: resetting the push rod to a top end position; driving the push rod; measuring the DC drive current in real time; recording a first position of the push rod at the start of a first abrupt change in the DC drive current when the first abrupt change in the DC drive current is detected and lasts for more than a first preset time period; continuing to drive the push rod and measure the DC drive current in real time; recording a second position of the push rod at the start of a second abrupt change; and calculating the stroke length of the valve based on the first position and the second position.

Abstract: A method includes providing a structure having two fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over each of the fins; a dielectric fin oriented lengthwise parallel to the fins and disposed between the two fins and over the isolation structure; a dummy gate stack over the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench; trimming the dielectric fin to reduce a width of the dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench.

Abstract: An atomization core includes: a substrate; and a heating element in contact with the substrate, the heating element including SS316L heating wires and two electrode connecting portions. The SS316L heating wires heat an aerosol generation substrate. The two electrode connecting portions are electrically connectable to a power supply. The two electrode connecting portions are arranged at an interval. The SS316L heating wires are bent and extend to be connected to the two electrode connecting portions.

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, an isolation feature embedded in the substrate and laterally between the first and second semiconductor channels, a first liner layer laterally surrounding the isolation feature between the isolation feature and the first semiconductor channel, and a second liner layer laterally surrounding the first liner layer between the first liner layer and the first semiconductor channel.

Abstract: The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer.

Abstract: A display driving method and a display device are provided. The display driving method includes following steps: obtaining frame data of a current frame; driving a first pixel according to a first grayscale value corresponding to the first pixel in the frame data; determining whether a second grayscale value corresponding to a second pixel in the frame data is significantly different from the first grayscale value corresponding to the first pixel; obtaining a new second grayscale value when the second grayscale value is significantly different from the first grayscale value; and driving the second pixel according to the new second grayscale value. The display driving method and display device of the disclosure may achieve good display effects.

Abstract: A fin field effect transistor device structure includes a substrate, an isolation structure, a first fin structure, a fin top layer, a first oxide layer, and a first gate structure. The first fin structure is disposed in the substrate and includes a base portion, a top portion, and a joint portion. The base portion is surrounded by the isolation structure. The top portion is exposed from the isolation structure. The joint portion connects the top portion and the base portion. The fin top layer is disposed over the top portion of the first fin structure. The fin top layer and the top portion of the first fin structure are made of different materials. The first oxide layer covers the fin top layer, the first fin structure, and the isolation structure. The first gate structure is disposed over the first oxide layer.

Abstract: Optical sensors and their making methods are described herein. In some embodiments, a described sensing apparatus includes: an image sensor; a collimator above the image sensor, wherein the collimator includes an array of apertures; and an optical filtering layer above the collimator, wherein the optical filtering layer is configured to filter a portion of light to be transmitted into the array of apertures.

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

Abstract: A computer-implemented method, comprising: dividing a first binary image into a plurality of variable-sized chunks, wherein the first binary image is an aggregate of a plurality of files, and wherein the dividing does not depend on file boundaries; and computing hashes of the variable-sized chunks, and storing the hashes in a content addressable storage (CAS) with the hashes as keys.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures suspended over a substrate and multiple second semiconductor nanostructures suspended over the substrate. The semiconductor device structure also includes a dielectric fin between the first semiconductor nanostructures and the second semiconductor nanostructures. The semiconductor device structure further includes a metal gate stack wrapped around the dielectric fin, the first semiconductor nanostructures and the second semiconductor nanostructures. The metal gate stack has a gate dielectric layer and a gate electrode, and the gate dielectric layer extends along a sidewall and a topmost surface of the dielectric fin.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures stacked in a vertical direction over a substrate, and a first dielectric structure between the first nanostructures and the second nanostructures. The semiconductor device structure includes a first gate structure formed over the first nanostructures. The first gate structure comprises a gate dielectric layer, and a topmost surface of the gate dielectric layer is higher than a top surface of the first dielectric structure.

Abstract: A device includes a substrate and a fin isolation structure between a first gate structure and a second gate structure. The first gate structure wraps around a first vertical stack of nanostructure channels overlying a first fin. The second gate structure wraps around a second vertical stack of nanostructure channels overlying a second fin. The fin isolation structure extends from an upper surface of the first gate structure to an upper surface of the substrate. A trench isolation structure is between the first fin and the fin isolation structure, and has different etch selectivity than the fin isolation structure.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a first dielectric feature separating the gate structure into a first portion and a second portion. The semiconductor structure also includes a metal layer formed over the gate structure. In addition, top surfaces of the first portion and the second portion of the gate structure and a top surface of the first dielectric feature are covered by the metal layer.

Abstract: A method and apparatus for entering a sleep mode, a storage medium and a user equipment are provided. The method includes: monitoring a Physical Downlink Control Channel (PDCCH) and determining whether to enter a sleep mode, wherein entering the sleep mode includes skipping a duration of PDCCH monitoring occasions or modifying PDCCH configuration.

Abstract: According to one example, a semiconductor structure includes a fin-shaped structure, a gate structure disposed over a region of the fin-shaped structure and having a sidewall including a lower portion and an upper portion above the lower portion, a first dielectric sidewall structure disposed along the lower portion of the sidewall, a second dielectric sidewall structure disposed along the upper portion of the sidewall and disposed on the first dielectric sidewall structure, and a source/drain feature disposed over a source/drain region of the fin-shaped structure and adjacent to the gate structure. The source/drain feature is separated from the gate structure by the first dielectric sidewall structure and the second dielectric sidewall structure. The first dielectric sidewall structure includes a different material than the second dielectric sidewall structure.

Abstract: Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

Abstract: A heat conduction plate assembly structure (1) includes a heat conduction plate (10) and a buffer pad (20). The heat conduction plate (10) includes a platform (11). The platform (11) includes an arc surface (111) attached to the heat-generating component (2) and an overflow slot (112) located on a side of the arc surface (111). The buffer pad (20) is fixed on the platform (11) and surrounds an outer side of the overflow slot (112). Therefore, a heat conduction plate assembly structure (1) with a desirable thermal conduction effect is provided to prevent the thermal conducting medium (50) from overflowing.

Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.