Patents by Inventor Cheng Peng

Cheng Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10977417
    Abstract: A structure includes first, second, third, and fourth conductive segments, and a gate. The first and second conductive segments are in a first conductive layer and configured as first and second terminals of a first transistor of a first type. The third and fourth conductive segments are in a second conductive layer stacked over the first conductive layer and configured as first and second terminals of a second transistor of a second type. The first gate is arranged, in a first direction, between the first and third conductive segments and the second and fourth conductive segments. The gate is configured as a control terminal of the first transistor and a control terminal of the second transistor, the first conductive segment is offset from the third conductive segment along the first direction, and the second conductive segment is offset from the fourth conductive segment along the first direction.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Patent number: 10977421
    Abstract: A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien
  • Patent number: 10969853
    Abstract: A USB adapting circuit is suitable for being connected between a USB host and an external device. The USB adapting circuit includes a connecting port, a detecting circuit, a standby circuit and a main circuit. The standby circuit receives a power supply from the USB host and supplies the detecting circuit and the main circuit with the power supply. The detecting circuit is configured to output a connected signal when the external device is connected to the connecting port. The standby circuit outputs an enabling signal in response to the connected signal. The main circuit adapts between the USB host and the external device when receiving the enabling signal. Therefore, the main circuit does not work without receiving the enabling signal, and has a power saving effect.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: April 6, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Cheng-Pin Chang, Tsung-Peng Chuang, Chun-Hao Peng
  • Patent number: 10967510
    Abstract: A robot arm processing system includes a robot arm, a processing module, and a control module. The robot arm is for providing a mechanical holding force. The processing module is disposed on the robot arm to process a workpiece. The control module is connected to the robot arm or the processing module. The control module outputs an anti-vibration signal according to the reaction force of the workpiece or the displacement of the robot arm to counteract the reaction force of the workpiece or the displacement of the robot arm.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: April 6, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Chen-Yu Kai, Kai-Ming Pan, Yen-Cheng Chen, Ta-Jen Peng
  • Publication number: 20210096155
    Abstract: The present disclosure relates to an in-situ testing device including a measuring head, a drive mechanism, and a testing chamber. The testing chamber is provided with a first optical observation hole. The measuring head is provided with a second optical observation hole. The testing chamber is provided with an opening allowing the measuring head to pass. The testing chamber is further provided with a shielding door, and the drive mechanism is connected to the shielding door to drive the shielding door to move relative to the testing chamber, to open or cover the opening, thereby opening or closing the testing chamber.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: QI-KUN XUE, XIAO-PENG HU, CHENG ZHENG, XI CHEN
  • Publication number: 20210098453
    Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei PENG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Li-Chun TIEN, Pin-Dai SUE, Wei-Cheng LIN
  • Patent number: 10962770
    Abstract: A computer implemented method for controlling camera exposure to augment a wiper system of a sensor enclosure. The computer implemented method can detect a presence of a wiper in one or more images captured by one or more cameras. An exposure time of the one or more cameras can be adjusted. Wiper speed can be adjusted such that wipers move in and out of one or more field of views of the one or more cameras while the one or more cameras are capturing images.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: March 30, 2021
    Assignee: Pony AI Inc.
    Inventors: Zhongnan Hu, Zuoteng Chen, Nengxiu Deng, Cheng Jin, Kai Chen, Yubo Zhang, Xiang Yu, Tiancheng Lou, Jun Peng
  • Patent number: 10964566
    Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Go., Ltd.
    Inventors: Tzu-Cheng Lin, Y.Y. Peng, Jerry Wang, Kewei Zuo, Chien Rhone Wang
  • Publication number: 20210091000
    Abstract: A method of manufacturing a semiconductor device including: arranging a first and a second gate strip separating in a first distance, wherein each of the first and the second gate strip is a gate terminal of a transistor; depositing a first contact via on the first gate strip; forming a first conductive strip on the first contact via, wherein the first conductive strip and the first gate strip are crisscrossed from top view; arranging a second and a third conductive strip, above the first conductive strip, separating in a second distance, wherein each of the second and the third conductive strip is free from connecting to the first conductive strip, the first and the second conductive strip are crisscrossed from top view. The first distance is twice as the second distance. A length of the first conductive strip is smaller than two and a half times as the first distance.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 25, 2021
    Inventors: SHIH-WEI PENG, HUI-TING YANG, WEI-CHENG LIN, JIANN-TYNG TZENG
  • Patent number: 10958992
    Abstract: Systems and methods for a scalable Open Shortest Path First (OSPF) deployment for optical networks include steps of causing communication to a router connected to a data communication network, for North-South communication; causing communication to a management plane associated with the optical network via one or more interfaces that are each connected to one or more Open Shortest Path First (OSPF) domains, for East-West communication; and implementing an OSPF terminator between the one or more OSPF domains that includes receiving OSPF packets, sending self-generated OSPF packets, and preventing flooding of received OSPF packets between the one or more OSPF domains.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: March 23, 2021
    Assignee: Ciena Corporation
    Inventor: Cheng Peng
  • Patent number: 10957611
    Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 23, 2021
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu
  • Patent number: 10943820
    Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, and depositing a first dielectric material on the first semiconductor fin and the second semiconductor fin on the semiconductor substrate using an atomic layer deposition process. There is a first trench between the first semiconductor fin and the second semiconductor fin. The method also includes filling the first trench with a flowable dielectric material, and heating the flowable dielectric material and the first dielectric material to form an isolation structure between the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Wei-Jin Li, Chung-Chi Ko, Yu-Cheng Shiau, Han-Sheng Weng, Chih-Tang Peng, Tien-I Bao
  • Patent number: 10936175
    Abstract: A computing device obtains multimedia content relating to a user of the computing device and generates a user interface. In a first mode of operation, the user interface displays a plurality of graphical thumbnails each depicting a cosmetic result, each graphical thumbnail corresponding to a cosmetic template, each of the plurality of cosmetic templates comprising a listing of cosmetic effects utilized for achieving each corresponding cosmetic result. A selection is obtained from the user of one or more graphical thumbnails to select one or more cosmetic templates. Responsive to operating in the second mode of operation, a corresponding listing of cosmetic effects is displayed for each of the one or more selected cosmetic templates and obtaining selection of one or more of the displayed cosmetic effects.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: March 2, 2021
    Assignee: PERFECT CORP.
    Inventors: Cheng Chou, Tsung-Peng Yen, Chieh-Chung Wu
  • Publication number: 20210057290
    Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang LIN, Chia-Cheng HO, Chun-Chieh LU, Cheng-Yi PENG, Chih-Sheng CHANG
  • Publication number: 20210058593
    Abstract: A projection device including a projection unit, an image capture device and a control unit is provided. The projection unit includes a light source. The projection unit is configured to project an image picture to a projection area. The image capture device is configured to obtain an image capture picture including the image picture in an image capture range. The image capture range is larger than the projection area. The control unit is coupled to the image capture device. The control unit is configured to determine, according to a picture variation value of the image capture picture, whether to adjust the brightness of the light source. In addition, a brightness adjusting method used for the projection device is also provided. According to the disclosure, the brightness of the light source of the projection device may be properly adjusted according to environmental factors.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 25, 2021
    Applicant: Coretronic Corporation
    Inventors: Chi-Wei Lin, Chien-Chun Peng, Hsun-Cheng Tu
  • Publication number: 20210027007
    Abstract: The present application provides an online document commenting method and apparatus. In an embodiment of the method, an operation of a user on a display interface is monitored, and a commenting behavior of commenting on a first document is recognized. The format of the first document is acquired when the commenting behavior is recognized, and the format of the first document is determined whether a pre-set format. The format of the first document is converted in order to generate a second document when the format of the first document is not the pre-set format, wherein the format of the second document is the pre-set format. The comment information regarding the second document is received and displayed. By means of the method, it is possible to present comment content to a user having a comment requirement, and not present the comment content to a user having no comment requirement.
    Type: Application
    Filed: November 1, 2018
    Publication date: January 28, 2021
    Inventor: Cheng PENG
  • Publication number: 20210028311
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Application
    Filed: October 12, 2020
    Publication date: January 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Shih-Wei Peng, Wei-Cheng Lin, Lei-Chun Chou
  • Patent number: 10900723
    Abstract: A cover defining an outer contour of a sensor enclosure with at least three identifiable portions stacked along a vertical axis. A first portion having a circular domed shape. A second portion, disposed underneath the first portion and coupled to a base of the first portion, having a truncated cone shape. The second portion includes one or more protruding grooves arranged diagonally about the vertical axis and imprinted on an outer surface of the second portion. The one or more protruding grooves channel a portion of an inlet airflow drawn into a cavity of the cover into a circular airflow. A third portion, disposed underneath the second portion and coupled to a base of the second portion, having a truncated cone shape.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: January 26, 2021
    Assignee: Pony AI Inc.
    Inventors: Zhongnan Hu, Zuoteng Chen, Nengxiu Deng, Cheng Jin, Kai Chen, Yubo Zhang, Xiang Yu, Tiancheng Lou, Jun Peng
  • Patent number: 10903198
    Abstract: A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 26, 2021
    Assignee: MEDIATEK INC
    Inventors: Chia-Cheng Chang, I-Hsuan Peng, Tzu-Hung Lin
  • Publication number: 20210018767
    Abstract: A reflective spatial light modulator (SLM) made of an electro-optic material, such as barium titanate, in a one-sided Fabry-Perot resonator can provide phase and/or amplitude modulation with fine spatial resolution at speeds over a Gigahertz. The light is confined laterally within the electro-optic material/resonator layer stack with microlenses, index perturbations, or by patterning the layer stack into a two-dimensional (2D) array of vertically oriented micropillars. Alternatively, a photonic crystal guided mode resonator can provide vertical and lateral confinement of the resonant mode. In phase-only modulation mode, each pixel in the SLM can produce a ? phase shift under a bias voltage below 10 V, while maintaining nearly constant reflection amplitude. The methodology for designing this SLM could also be used to design other SLMs (for example, amplitude-only SLMs).
    Type: Application
    Filed: May 18, 2020
    Publication date: January 21, 2021
    Inventors: Cheng PENG, Christopher Louis Panuski, Ryan HAMERLY, Dirk Robert ENGLUND