Abstract: An inspection apparatus is capable for inspecting at least one light-emitting device. The inspection apparatus includes a working machine and an inspection light source. The inspection light source is disposed on the working machine and located above the light-emitting device. A dominant wavelength of the inspection light source is smaller than a dominant wavelength of the light-emitting device so as to excite the light-emitting device and get an optical property of the light-emitting device.

Abstract: An inspection apparatus is capable of inspecting a light-emitting diode (LED). The inspection apparatus includes a reflecting cover, a base plate, a light-collecting unit and at least one inspection light source. An enclosed space is defined by the base plate and the reflecting cover having an opening. The LED is disposed on the base plate and located in the enclosed space. The light-collecting unit is disposed above the LED and in the enclosed space. A vertical distance from the light-collecting unit to the LED is H, a width of the opening of the reflecting cover is W, and H/W=0.05 to 10. The inspection light source is in the enclosed space. An inspection light emitted from the inspection light source is reflected by the reflecting cover and then emitted into the LED. A dominant wavelength of the inspection light source is smaller than that of the LED.

Abstract: A structure of a solar cell. The structure of the solar cell includes a substrate, a graded layer and a semiconductor layer. The graded layer is disposed on the substrate. The graded layer is made from materials including the first material and the second material, and includes at least one thin film. One of the at least one thin film includes a mixture of at least the first material and the second material at a mixture ratio. The mixture forms a bandgap of the at least one thin film. The semiconductor layer is disposed on the graded layer.

Abstract: A structure of a solar cell is provided. The structure of the solar cell includes a substrate, a base and a plurality of nanostructures. The base is disposed on the substrate. The nanostructures are disposed on a surface of the base, or a surface of the base includes the nanostructures, so as to increase light absorption of the structure.

Abstract: A POP (Package-On-Package) semiconductor device with encapsulating protection of soldered joints between the external leads, primarily comprises a plurality of stacked semiconductor packages and dielectric coating. Each semiconductor package includes at least a chip, a plurality of external leads of leadframe, and an encapsulant where the external leads are exposed and extended from a plurality of sides of the encapsulant. Terminals of a plurality external leads of a top semiconductor package are soldered to the soldered regions of the corresponding external leads of a bottom semiconductor package. The dielectric coating is disposed along the sides of the encapsulant of the bottom semiconductor package to connect the soldered points between the external leads and to partially or completely encapsulate the soldering materials so that the stresses between the soldered joints can be dispersed and no electrical shorts happen.

Abstract: A POP (Package-On-Package) semiconductor device with encapsulating protection of soldered joints between the external leads, primarily comprises a plurality of stacked semiconductor packages and dielectric coating. Each semiconductor package includes at least a chip, a plurality of external leads of leadframe, and an encapsulant where the external leads are exposed and extended from a plurality of sides of the encapsulant. Terminals of a plurality external leads of a top semiconductor package are soldered to the soldered regions of the corresponding external leads of a bottom semiconductor package. The dielectric coating is disposed along the sides of the encapsulant of the bottom semiconductor package to connect the soldered points between the external leads and to partially or completely encapsulate the soldering materials so that the stresses between the soldered joints can be dispersed and no electrical shorts happen.

Abstract: A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to the substrate. The encapsulant is formed above the upper surface of the substrate. The external terminals are disposed on the lower surface of the substrate. The stress release layer is formed on the interface of the substrate and the encapsulant such that the external terminals are movable with respect to the encapsulated chip. In addition, a fabrication process of the semiconductor package is also disclosed.

Abstract: A ball grid array package structure includes: a substrate having at least one chip bearing area on its upper surface and a plurality of electrical-connecting points on its lower surface; a plurality of chips are arranged on the chip bearing area and electrically connected with those electrical-connecting points; a plurality of through holes penetrating the substrate at the edge of chip bearing area; an encapsulant used to cover those chip and filling those through holes to form a strengthened bump surrounding the chip bearing area on the lower surface of the substrate; and a plurality of conductive balls are respectively arranged on those electrical-connecting points. The present invention utilizes the strengthened bump on the bottom of the substrate to enhance the structure strength of the substrate so as to avoid the warpage of the substrate caused from the stress due to the temperature variation during the package process to affect the following processes.

Abstract: A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to the substrate. The encapsulant is formed above the upper surface of the substrate. The external terminals are disposed on the lower surface of the substrate. The stress release layer is formed on the interface of the substrate and the encapsulant such that the external terminals are movable with respect to the encapsulated chip. In addition, a fabrication process of the semiconductor package is also disclosed.

Abstract: A package structure includes: a substrate having a chip-bearing area arranged thereon; an window type assistant element arranged on the substrate and surrounding the edge of the chip-bearing area; a plurality of chips arranged within the chip-bearing area; and a package encapsulation covering chips within the chip-bearing area. It can resist the deformation and reduce the damage from the warpage and simultaneously enhance the yield and stability of the package structure.