Patents by Inventor Cheng-Po CHAU

Cheng-Po CHAU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145581
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Chu LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Patent number: 11923235
    Abstract: A method includes forming a first trench and a second trench in a semiconductor substrate; forming a first mask over the semiconductor substrate, wherein the first mask is disposed in a first portion of the first trench and exposes the second trench and a second portion of the first trench; after forming the first mask, deepening the second trench and the second portion of the first trench; after deepening the second trench and the second portion of the first trench, removing the first mask; and after removing the first mask, filling a dielectric material in both the first and second trenches.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta Wu, Chii-Ming Wu, Sen-Hong Syue, Cheng-Po Chau
  • Patent number: 11901442
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Wen Chiu, Yi Che Chan, Lun-Kuang Tan, Zheng-Yang Pan, Cheng-Po Chau, Pin-Chu Liang, Hung-Yao Chen, De-Wei Yu, Yi-Cheng Li
  • Patent number: 11854800
    Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Szu-Ying Chen, Ya-Wen Chiu, Cheng-Po Chau, Yi Che Chan, Chih Ping Liao, YungHao Wang, Sen-Hong Syue
  • Publication number: 20230386832
    Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 30, 2023
    Inventors: Szu-Ying Chen, Ya-Wen Chiu, Cheng-Po Chau, Yi Che Chan, Chih Ping Liao, YungHao Wang, Sen-Hong Syue
  • Publication number: 20230386847
    Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 30, 2023
    Inventors: Hongfa Luan, Yi-Fan Chen, Chun-Yen Peng, Cheng-Po Chau, Wen-Yu Ku, Huicheng Chang
  • Publication number: 20230352563
    Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.
    Type: Application
    Filed: June 27, 2023
    Publication date: November 2, 2023
    Inventors: De-Wei Yu, Cheng-Po Chau, Yun Chen Teng
  • Patent number: 11776814
    Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hongfa Luan, Yi-Fan Chen, Chun-Yen Peng, Cheng-Po Chau, Wen-Yu Ku, Huicheng Chang
  • Patent number: 11728406
    Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: De-Wei Yu, Cheng-Po Chau, Yun Chen Teng
  • Patent number: 11677015
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Wen Chiu, Yi Che Chan, Lun-Kuang Tan, Zheng-Yang Pan, Cheng-Po Chau, Pin-Ju Liang, Hung-Yao Chen, De-Wei Yu, Yi-Cheng Li
  • Publication number: 20220376079
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Hung-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
  • Publication number: 20220376091
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Ju LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Publication number: 20220367248
    Abstract: A method includes forming a first trench and a second trench in a semiconductor substrate; forming a first mask over the semiconductor substrate, wherein the first mask is disposed in a first portion of the first trench and exposes the second trench and a second portion of the first trench; after forming the first mask, deepening the second trench and the second portion of the first trench; after deepening the second trench and the second portion of the first trench, removing the first mask; and after removing the first mask, filling a dielectric material in both the first and second trenches.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta WU, Chii-Ming WU, Sen-Hong SYUE, Cheng-Po CHAU
  • Patent number: 11450555
    Abstract: A method includes forming a first trench in a semiconductor substrate. A mask is filled in the first trench and over the semiconductor substrate. After filling the mask in the first trench, the mask is patterned to form an opening in the mask. A second trench is formed in the semiconductor substrate. A depth of the second trench is different from a depth of the first trench. After forming the second trench in the semiconductor substrate, the mask is removed. A dielectric material is filled in both the first and second trenches.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta Wu, Chii-Ming Wu, Sen-Hong Syue, Cheng-Po Chau
  • Patent number: 11444173
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Jin-Mu Yin, Tsung-Chieh Hsiao, Chia-Lin Chuang, Li-Zhen Yu, Dian-Hau Chen, Shih-Wei Wang, De-Wei Yu, Chien-Hao Chen, Bo-Cyuan Lu, Jr-Hung Li, Chi-On Chui, Min-Hsiu Hung, Hung-Yi Huang, Chun-Cheng Chou, Ying-Liang Chuang, Yen-Chun Huang, Chih-Tang Peng, Cheng-Po Chau, Yen-Ming Chen
  • Patent number: 11211470
    Abstract: An improved dummy gate and a method of forming the same are disclosed. In an embodiment, the method includes depositing a first material in a trench, the trench being disposed between a first fin and a second fin; etching the first material to expose an upper portion of sidewalls of the trench; and depositing a second material on the first material without the second material being deposited on the exposed upper portion of the sidewalls of the trench.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Ku Chen, Chii-Horng Li, Cheng-Po Chau, Pei-Ren Jeng, Yee-Chia Yeo, Chia-Ao Chang
  • Publication number: 20210366715
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Ta-Chun Ma, Yi-Cheng Li, Pin-Ju Liang, Cheng-Po Chau, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Cheng-Hsiung Yen
  • Publication number: 20210359111
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: December 2, 2020
    Publication date: November 18, 2021
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Ju LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Publication number: 20210280414
    Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 9, 2021
    Inventors: Szu-Ying Chen, Ya-Wen Chiu, Cheng-Po Chau, Yi Che Chan, Chih Ping Liao, YungHao Wang, Sen-Hong Syue
  • Patent number: 11087987
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun Ma, Yi-Cheng Li, Pin-Ju Liang, Cheng-Po Chau, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Cheng-Hsiung Yen