Patents by Inventor Cheng Shen

Cheng Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240417505
    Abstract: A two-component polyurethane composition contains (A) an aqueous dispersion comprising: a hydroxyl group-containing acrylic emulsion polymer comprising, by weight based on the weight of the hydroxyl group-containing acrylic emulsion polymer, from 5% to 50% of structural units of a hydroxy-functional alkyl (meth) acrylate; and from 2% to 20%, by weight based on the weight of the hydroxyl group-containing acrylic emulsion polymer, of a branched polyether polyol; where the branched polyether polyol has a hydroxyl functionality of from 4 to 10 and a molecular weight per branch of from 1200 to 2500 grams per mole, and contains from 20% to 40% of ethylene oxide units, by weight based on the weight of the branched polyether polyol; and (B) a polyisocyanate.
    Type: Application
    Filed: December 23, 2021
    Publication date: December 19, 2024
    Inventors: Daoshu Lin, Cheng Shen, Yan Li, Jia Tang
  • Publication number: 20240384408
    Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Ting TSAI, Chung-Liang CHENG, Wen-Cheng CHENG, Che-Hung LIU, Yu-Cheng SHEN, Chyi-Tsong NI
  • Publication number: 20240387633
    Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The semiconductor device also includes a gate structure that includes first and second portions. The first portion is formed between each nanostructure of nanostructures. The second portion is formed under the bottom-most nanostructure of the plurality of nanostructures and extends under a top surface of the substrate.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Cheng SHEN, Guan-Jie Shen
  • Publication number: 20240368472
    Abstract: A surfactant composition includes 60 wt % or greater of a surfactant based on a total weight of the surfactant composition and 0.01 wt % to 5 wt % of a hydroxyl amine having structure (I) based on the total weight of the surfactant composition, wherein R1, R2 and R3 of Structure (I) are independently selected from the group consisting of H, an alkanolamine, or a hydroxyl alkyl group with linear or branched carbon chain having from 1 to 8 carbons, and R4 of Structure (I) is selected from the group consisting of an alkanolamine, or a hydroxyl alkyl group with linear or branched carbon chain having from 1 to 8 carbons.
    Type: Application
    Filed: October 6, 2021
    Publication date: November 7, 2024
    Inventors: Cheng Shen, Haiying Li, Shaoguang Feng, Jian Zou, Wanglin Yu
  • Patent number: 12129399
    Abstract: A freeze-thaw stabilizer additive composition including (a) at least one anti-freezing agent; and (b) at least one emulsifier; and (c) any other desired optional compound; a process for making the above freeze-thaw stabilizer additive composition, a paint formulation made containing the above freeze-thaw stabilizer additive composition; and a process for making the above paint formulation.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: October 29, 2024
    Assignee: Dow Global Technologies LLC
    Inventors: Ling Zhong, Jing Ji, Cheng Shen, Jianhai Mu
  • Publication number: 20240353665
    Abstract: Embodiments pertain to angular ptychographic imaging with closed-form imaging methods. computer products and imaging systems.
    Type: Application
    Filed: March 29, 2024
    Publication date: October 24, 2024
    Inventors: Ruizhi Cao, Cheng Shen, Changhuei Yang
  • Patent number: 12124308
    Abstract: Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a method increases an operation voltage of one or more processors, based at least in part, on one or more error rates of the one or more processors.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: October 22, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Benjamin D. Faulkner, Padmanabhan Kannan, Srinivasan Raghuraman, Peng Cheng Shen, Divya Ramakrishnan, Swanand Santosh Bindoo, Sreedhar Narayanaswamy, Amey Y. Marathe
  • Patent number: 12107440
    Abstract: Embodiments of the invention provide a power supply control method and a monitor system capable of executing the power supply control method. The monitor system includes a base station, an image capture apparatus, and a processor. The base station includes a charging apparatus including a power supply connector and a power source coupled to the power supply connector and outputting power through the power supply connector. The image capture apparatus shoots the power supply connector to obtain a shot image. The processor determines a foreign object distribution on the power supply connector according to the shot image and sends a warning message according to the foreign object distribution. The foreign object distribution relates to foreign objects formed on the power supply connector. Accordingly, whether a charging mechanism fails can be automatically determined and notification and/or compensation may be performed when the charging mechanism fails.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: October 1, 2024
    Assignee: Coretronic Intelligent Robotics Corporation
    Inventors: Cheng-Shen Lee, Chih-Neng Tseng, Kuan-Chou Ko
  • Publication number: 20240309273
    Abstract: A surfactant composition includes 60 wt % or greater of a surfactant based on a total weight of the surfactant composition. 0.01 wt % to 1 wt % of an antioxidant, and 0.01 wt % to 5 wt % of a hydroxyl amine having structure (I) based on the total weight of the surfactant composition wherein R1, R2 and R3 of Structure (I) are independently selected from the group consisting of H, an alkanolamine, or a hydroxyl alkyl group with linear or branched carbon chain having from 1 to 8 carbons, and R4 of Structure (I) is selected from the group consisting of an alkanolamine, or a hydroxyl alkyl group with linear or branched carbon chain having from 1 to 8 carbons.
    Type: Application
    Filed: October 6, 2021
    Publication date: September 19, 2024
    Inventors: Qianyuan Shan, Cheng Shen, Jian Zou, Zhouhua Ji, Shuyu Duan, Hongying Wang
  • Patent number: 12091752
    Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ting Tsai, Chung-Liang Cheng, Wen-Cheng Cheng, Che-Hung Liu, Yu-Cheng Shen, Chyi-Tsong Ni
  • Publication number: 20240295606
    Abstract: Disclosed are a method and a system for battery parameter update. The method is adapted to update a first battery parameter set of a target battery module, and includes: collecting a plurality of second battery parameter sets to a server when updating of a plurality of other battery modules are completed; classifying the second battery parameter sets based on a collection condition and storing them as reference battery parameter sets; determining whether the target battery module has not updated the first battery parameter set for more than a specified time; selecting a suitable battery parameter set close to a use state of the target battery module from the reference battery parameter sets when the target battery module does not update the first battery parameter set for more than the specified time; and updating the first battery parameter set of the target battery module according to the suitable battery parameter set.
    Type: Application
    Filed: November 6, 2023
    Publication date: September 5, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Ke-Jen Hung, Yu-Cheng Shen
  • Publication number: 20240294831
    Abstract: A surfactant composition includes 60 wt % or greater of a surfactant based on a total weight of the surfactant composition and 0.01 wt % to 1 wt % of a hydrazide antioxidant.
    Type: Application
    Filed: October 6, 2021
    Publication date: September 5, 2024
    Inventors: Cheng Shen, Haiying Li, Shaoguang Feng, Jian Zou, Zeyu Zhong, Qianyuan Shan
  • Publication number: 20240286889
    Abstract: A method for forming a semiconductor structure includes following operations. An interconnect structure is formed over a substrate. The interconnect structure includes a top conductive layer. A dielectric structure is formed over the interconnect structure. The dielectric structure is patterned to simultaneously form a cavity and a protrusion in the cavity. A MEMS substrate is bonded to the dielectric structure to seal the cavity. The protrusion is separated from the MEMS substrate.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Inventors: CHING-KAI SHEN, JUNG-KUO TU, WEI-CHENG SHEN, YI-CHUAN TENG
  • Publication number: 20240265549
    Abstract: The present disclosure may provide a marking system for intestinal valve imaging. The marking system may obtain multiple intestinal images of an examined object. The marking system may perform intestinal valve segmentation on at least a portion of the multiple intestinal images to determine at least one independent intestinal valve. The marking system may also mark the at least one independent intestinal valve in the at least a portion of the multiple intestinal images.
    Type: Application
    Filed: May 25, 2023
    Publication date: August 8, 2024
    Applicant: KEYWESTTECH LLC.
    Inventors: Shi WANG, Cheng SHEN, Huogen WANG, Chaohui JIN, Ming CHEN
  • Publication number: 20240266236
    Abstract: An electronic package module and the method for fabrication of the same are provided. The method for fabricating the electronic package module includes providing a circuit substrate. An interposer frame and a first electronic component are disposed on the circuit substrate, and a shielding material with an opening overlapping the electronic component is disposed on the interposer frame. Subsequently, with the shielding material being as a mask, the molding material is filled into through the opening, thereby forming the molding layer encapsulating the electronic component. After forming the molding layer, the shielding material is removed, so that an interface of the interposer frame is exposed. Therefore, the solder ball can be disposed on the interface of the interposer frame without further machining of the molding layer.
    Type: Application
    Filed: July 19, 2023
    Publication date: August 8, 2024
    Inventors: LI-CHENG SHEN, Chao-Hsuan Wang
  • Publication number: 20240266295
    Abstract: An electronic package module and the method for fabrication of the same are provided. The method includes providing a circuit substrate with a first surface. An interposer frame and at least one first electronic component are disposed on the first surface. Subsequently, a first molding layer encapsulating the first electronic component and the interposer frame is formed on the first surface. A shielding material is disposed on the first molding layer, and thus the shielding material covers the interposer frame while the opening of the shielding material overlaps the electronic component. With the shielding material as the mask, a heat conductive solder is deposited on the first molding layer. After removing the shielding material, the interposer frame is connected to a main board. Therefore, the heat dissipation of the electronic component toward the main board accelerates due to the heat conductive solder.
    Type: Application
    Filed: June 16, 2023
    Publication date: August 8, 2024
    Inventor: LI-CHENG SHEN
  • Patent number: 12056860
    Abstract: The present invention discloses an image processing method. The image processing method includes the following steps: (a), a to-be-processed image is corrected as a first correction image according to a first mapping relationship along a correction direction; (b) the first correction image by an angle is rotated; and (c) the rotated first correction image is corrected as a second correction image according to a second mapping relationship along the same correction direction. In embodiment, given that the to-be-processed image is deformed along two different directions, the to-be-processed image is corrected along the same correction direction, such that correction complexity could be reduced.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: August 6, 2024
    Assignee: CVITEK CO. LTD.
    Inventors: Bang-Sian Liu, Ju-Yu Yu, Jen-Shi Wu, Bau-Cheng Shen
  • Patent number: 12024581
    Abstract: A polyurethane composition reaction mixture including: (a) at least one organic isocyanate; and (b) at least one butylene oxide-based hydrophobic polyol; a process for making the above polyurethane composition; a polyurethane composite article composition, a process for making the above polyurethane composite article composition; and a process for making a composite article from the above polyurethane composite article composition.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 2, 2024
    Assignee: Dow Global Technologies LLC
    Inventors: Hua Ren, Beilei Wang, Huan Chen, Yongchun Chen, Dong Yun, Cheng Shen
  • Patent number: 12017908
    Abstract: A semiconductor structure includes a substrate, a MEMS substrate, a dielectric structure between the substrate and the MEMS substrate, a cavity in the dielectric structure, an electrode over the substrate, and a protrusion disposed in the cavity. The MEMS substrate includes a movable membrane, and the cavity is sealed by the movable membrane. A height of the protrusion is less than a depth of the cavity.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Kai Shen, Jung-Kuo Tu, Wei-Cheng Shen, Yi-Chuan Teng
  • Patent number: 12010812
    Abstract: A dust-proof telecommunication system is disclosed. The dust-proof telecommunication system includes a chassis, critical components located within the chassis, and a filter module located within the chassis near at least some of the critical components that need to be cooled. For example, the critical components include a central processing unit (CPU), a system on chip (SoC), a memory module, a PCIe card, and/or a chipset. The filter module has a filter cover that surrounds at least in part the critical components, a first air filter located at an inlet of an airflow, and a second air filter located at an outlet. The critical components located at a protective space within the chassis receive and are cooled by the airflow passing through the air filter.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: June 11, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yi-Chieh Chen, Yueh-Chang Wu, Ching-Yi Shih, Po-Cheng Shen