Patents by Inventor Cheng-ta Wu

Cheng-ta Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250081570
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC). The IC includes a pair of source/drain regions in a substrate. A gate dielectric layer is on the substrate and laterally between the source/drain regions. A gate electrode overlies the gate dielectric layer. A sidewall liner is disposed along sidewalls of the gate electrode and along an upper surface of the substrate. A sidewall spacer overlies the substrate and is on sidewalls and an upper surface of the sidewall liner. The sidewall spacer has a pair of segments respectively on opposite sides of the gate electrode. The sidewall spacer consists essentially of silicon oxycarbonitride. A dielectric constant of the sidewall spacer is greater than that of the sidewall liner.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 6, 2025
    Inventor: Cheng-Ta Wu
  • Patent number: 12211877
    Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ta Wu, Kuo-Hwa Tzeng, Yeur-Luen Tu
  • Patent number: 12183804
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC). The IC includes a pair of source/drain regions in a substrate. A gate dielectric layer is on the substrate and laterally between the source/drain regions. A gate electrode overlies the gate dielectric layer. A sidewall liner is disposed along sidewalls of the gate electrode and along an upper surface of the substrate. A sidewall spacer overlies the substrate and is on sidewalls and an upper surface of the sidewall liner. The sidewall spacer has a pair of segments respectively on opposite sides of the gate electrode. The sidewall spacer consists essentially of silicon oxycarbonitride. A dielectric constant of the sidewall spacer is greater than that of the sidewall liner.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Cheng-Ta Wu
  • Patent number: 12165911
    Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuan-Liang Liu, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 12148756
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Po-Wei Liu, Yeur-Luen Tu, Yu-Chun Chang
  • Publication number: 20240379712
    Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Cheng-Ta Wu, Kuo-Hwa Tzeng, Yeur-Luen Tu
  • Publication number: 20240379684
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Po-Wei Liu, Yeur-Luen Tu, Yu-Chun Chang
  • Publication number: 20240355618
    Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Inventors: Cheng-Ta Wu, Chia-Ta Hsieh, Kuo Wei Wu, Yu-Chun Chang, Ying Ling Tseng
  • Publication number: 20240347377
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
  • Patent number: 12119267
    Abstract: A method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng Chou, Shiu-Ko Jangjian, Cheng-Ta Wu
  • Patent number: 12100767
    Abstract: A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ta Wu, Chii-Ming Wu, Shiu-Ko Jangjian, Kun-Tzu Lin, Lan-Fang Chang
  • Patent number: 12087206
    Abstract: A color adjustment device applied to a display panel includes a first controller and a second controller. The first controller is configured to control light emission of the display panel. The second controller is connected to the first controller, and is configured to receive an input image, and determine whether a blue component proportion of the input image is greater than a preset proportion and whether luminance of the display panel is lower than a luminance threshold value, wherein at least one pulse signal is transmitted from the second controller to the first controller through a first signal line when the blue component proportion is greater than the preset proportion and the luminance of the display panel is lower than the luminance threshold value.
    Type: Grant
    Filed: August 3, 2022
    Date of Patent: September 10, 2024
    Assignee: WISTRON CORP.
    Inventors: Chang Lin Liou, Chih Hao Lo, Cheng Ta Wu
  • Patent number: 12074036
    Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Chen-Hao Chiang, Alexander Kalnitsky, Yeur-Luen Tu, Eugene Chen
  • Publication number: 20240274659
    Abstract: A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.
    Type: Application
    Filed: April 11, 2024
    Publication date: August 15, 2024
    Inventors: Cheng-Ta Wu, Chiu Hua Chen
  • Patent number: 12062539
    Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: August 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ta Wu, Chia-Ta Hsieh, Kuo Wei Wu, Yu-Chun Chang, Ying Ling Tseng
  • Patent number: 12040221
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
  • Publication number: 20240170524
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first substrate having a front-side and a back-side opposite the front-side. A first doped region is in the first substrate and extends continuously from the front-side to the back-side. A conductive contact is over the first doped region. A conductive layer is between the first doped region and the conductive contact. The first doped region abuts a lower surface and sides of the conductive layer.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Inventors: Min-Ying Tsai, Cheng-Ta Wu, Yeur-Luen Tu
  • Patent number: 11984477
    Abstract: A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Ta Wu, Chui Hua Chen
  • Publication number: 20240154023
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC). The IC includes a pair of source/drain regions in a substrate. A gate dielectric layer is on the substrate and laterally between the source/drain regions. A gate electrode overlies the gate dielectric layer. A sidewall liner is disposed along sidewalls of the gate electrode and along an upper surface of the substrate. A sidewall spacer overlies the substrate and is on sidewalls and an upper surface of the sidewall liner. The sidewall spacer has a pair of segments respectively on opposite sides of the gate electrode. The sidewall spacer consists essentially of silicon oxycarbonitride. A dielectric constant of the sidewall spacer is greater than that of the sidewall liner.
    Type: Application
    Filed: January 3, 2024
    Publication date: May 9, 2024
    Inventor: Cheng-Ta Wu
  • Patent number: 11955496
    Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ta Wu, Kuo-Hwa Tzeng, Yeur-Luen Tu