Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: The present invention relates to a multicomponent-alloy material layer and a method of manufacturing the multicomponent-alloy material layer and a capacitor structure of a semiconductor device comprising the multicomponent-alloy material layer. The multicomponent-alloy material layer has four to six metal elements and has specific two kinds of metal components, and the two kinds of metal components have a specific content ratio, such that without a thermal annealing treatment, the multicomponent-alloy material layer has a specific work function for an application in the capacitor structure of the semiconductor device.

Abstract: A color adjustment device applied to a display panel includes a first controller and a second controller. The first controller is configured to control light emission of the display panel. The second controller is connected to the first controller, and is configured to receive an input image, and determine whether a blue component proportion of the input image is greater than a preset proportion and whether luminance of the display panel is lower than a luminance threshold value, wherein at least one pulse signal is transmitted from the second controller to the first controller through a first signal line when the blue component proportion is greater than the preset proportion and the luminance of the display panel is lower than the luminance threshold value.

Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor structure. The method includes forming a plurality of bulk micro defects within a handle substrate. Sizes of the plurality of bulk micro defects are increased to form a plurality of bulk macro defects (BMDs) within the handle substrate. Some of the plurality of BMDs are removed from within a first denuded region and a second denuded region arranged along opposing surfaces of the handle substrate. An insulating layer is formed onto the handle substrate. A device layer comprising a semiconductor material is formed onto the insulating layer. The first denuded region and the second denuded region vertically surround a central region of the handle substrate that has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

Abstract: A method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.

Abstract: A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.

Abstract: A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.

Abstract: A method for manufacturing a semiconductor structure includes etching trenches in a semiconductor substrate to form a semiconductor fin between the trenches; converting sidewalls of the semiconductor fin into hydrogen-terminated surfaces each having silicon-to-hydrogen (S—H) bonds; after converting the sidewalls of the semiconductor fin into the hydrogen-terminated surfaces, depositing a dielectric material overfilling the trenches; and etching back the dielectric material to fall below a top surface of the semiconductor fin.

Abstract: A method includes forming a first trench and a second trench in a semiconductor substrate; forming a first mask over the semiconductor substrate, wherein the first mask is disposed in a first portion of the first trench and exposes the second trench and a second portion of the first trench; after forming the first mask, deepening the second trench and the second portion of the first trench; after deepening the second trench and the second portion of the first trench, removing the first mask; and after removing the first mask, filling a dielectric material in both the first and second trenches.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a handle substrate having a plurality of bulk macro defects (BMDs). An insulating layer is disposed onto a top surface of the handle substrate. A device layer, including a semiconductor material, is disposed onto the insulating layer. The handle substrate has a first denuded region and a second denuded region that vertically surround a central region of the handle substrate. The central region has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

Abstract: A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a through substrate via (TSV) in a first substrate. The TSV continuously extends from a first surface of the first substrate to a second surface of the first substrate. A conductive contact is formed on the second surface of the first substrate. The conductive contact comprises a first conductive layer disposed on the TSV. An upper conductive layer is formed between the conductive contact and the TSV. The upper conductive layer comprises a silicide of a conductive material of the first conductive layer.