Abstract: An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may detect a trigger event associated with a satellite communication link, the trigger event being based at least in part on at least one of: a status of an access link associated with the UE, or information associated with another device or a component of the UE. The UE may transmit a communication via the satellite communication link based at least in part on detecting the trigger event. Numerous other aspects are described.

Abstract: A semiconductor structure includes a substrate, a plurality of gates, a cut isolation structure, and an interlayer dielectric layer. The plurality of gates are formed on the substrate. The plurality of gates extend along a first direction. The cut isolation structure is formed on the substrate. The cut isolation structure passes through the gates in a second direction. A size of the cut isolation structure in the first direction is equal to a predetermined size. The second direction is different from the first direction. The interlayer dielectric layer is formed on the substrate. The interlayer dielectric layer surrounds the gates and the cut isolation structure.

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for power leakage mitigation in transmit diversity. A method of controlling transmit diversity includes detecting that a first compensator among a plurality of compensators is 2024/138489 in transmit mode; outputting a first control signal to the first compensator to enable the first compensator for transmit mode in response to detecting that the first compensator is in transmit mode; and outputting a second control signal to a second compensator among the plurality of compensators to disable the second compensator from operating in transmit mode in response to detecting that the first compensator is in transmit mode.

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region.

Abstract: Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.

Abstract: Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.

Abstract: Techniques are provided for making asymmetric contacts to improve the performance of thin film transistors (TFT) structures. The asymmetry may be with respect to the area of contact interface with the semiconductor region and/or the depth to which the contacts extend into the semiconductor region. According to some embodiments, the TFT structures are used in memory structures arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include asymmetric contacts, such as two contacts that each have a different contact area to a semiconductor region, and/or that extend to different depths within the semiconductor region. The degree of asymmetry may be tuned during fabrication to modulate certain transistor parameters such as, for example, leakage, capacitance, gate control, channel length, or contact resistance.

Abstract: A displaying base plate includes an active area and a non-active area connected thereto. The non-active area includes an edge region and a first-dam region located between the active area and the edge region. The displaying base plate includes: a substrate, and an anti-static layer provided on the substrate and located at least within the edge region. The edge region includes a cutting-transition region, a crack-dam region and a driving-circuit region. The crack-dam region surrounds the first-dam region, and is broken at the driving-circuit region. The cutting-transition region surrounds the crack-dam region and the driving-circuit region. The displaying base plate includes a first planarization part located within the cutting-transition region and the crack-dam region, and a first protrusion located within the crack-dam region. The first protrusion is provided on one side of the first planarization part away from the substrate, and the anti-static layer covers the first protrusion.

Abstract: A semiconductor structure includes: a substrate; channel structures on the substrate, a channel structure of the channel structures including a plurality of channel layers stacked along a direction perpendicular to a surface of the substrate and a plurality of gate grooves between adjacent channel layers; gate structures spanning the channel structure, the gate structures being also in the plurality of gate grooves; source/drain regions on the substrate on two sides of the gates and the channel layers, the source/drain regions being in contact with sidewalls of a plurality of channel layers; and inner spacer layers between adjacent channel layers, and first dielectric layers between the inner spacer layers and the gate structures, the inner spacer layers being between the source/drain regions and the gate structures.

Abstract: The present application provides a displaying base plate and a displaying device, which relates to the technical field of displaying. The displaying device can ameliorate the problem of screen greening caused by electrostatic charges, thereby improving the effect of displaying. The displaying base plate includes an active area and a non-active area connected to the active area, the non-active area includes an edge region and a first-dam region, and the first-dam region is located between the active area and the edge region; the displaying base plate further includes: a substrate; an anti-static layer disposed on the substrate, wherein the anti-static layer is located at least within the edge region; and a driving unit and a touch unit that are disposed on the substrate, wherein the driving unit is located within the active area.

Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.

Abstract: A system for synchronizing an electrical generator to a reference power source, the system comprising: a first measurement unit configured to: measure a magnitude and a frequency of a first electrical power at a terminal of the reference power source; record first timing data indicative of the occurrence of predetermined variations of the first electrical power at the terminal of the reference power source; and transmit the first timing data and first measurement data comprising the measured magnitude and the measured frequency of the first electrical power; a second measurement unit configured to: receive the first measurement data; measure a magnitude and a frequency of a second electrical power at a terminal of the electrical generator; and record second timing data indicative of a present time; and a controller configured to adjust operational characteristics of the electrical generator based on the first timing data, the second timing data, the first measurement data, and second measurement data comprisi

Abstract: An envelope detection circuit and methods for detecting an envelope of a signal using such an envelope detection circuit. One example envelope detection circuit generally includes a first diode, a capacitive element, and a clamping circuit. The first diode has an anode coupled to an input node of the envelope detection circuit and has a cathode coupled to an output node of the envelope detection circuit. The capacitive element is coupled in shunt between the output node and a reference potential node, and the clamping circuit is coupled in shunt between the input node and the reference potential node. The clamping circuit generally includes a resistive element coupled in series with a second diode.

Abstract: An apparatus and method to oxidize a contaminant entrained in potable water. The method can include a step of adding an amount of at least one of hydrogen peroxide (H2O2), hypochlorous acid (HOCl), or chloramine (NH2Cl) to the potable water to form a solution. The method can include a step of exposing the solution to a source of UV radiation to form a catalyst including at least one of a hydroxyl radical, a reactive chlorine species, or a reactive amine species to oxidize the inorganic contaminant.

Abstract: The present application provides a displaying base plate and a displaying device, which relates to the technical field of displaying. The displaying device can ameliorate the problem of screen greening caused by electrostatic charges, thereby improving the effect of displaying. The displaying base plate includes an active area and a non-active area connected to the active area, the non-active area includes an edge region and a first-dam region, and the first-dam region is located between the active area and the edge region; the displaying base plate further includes: a substrate; an anti-static layer disposed on the substrate, wherein the anti-static layer is located at least within the edge region; and a driving unit and a touch unit that are disposed on the substrate, wherein the driving unit is located within the active area.

Abstract: The present application provides a displaying base plate and a displaying device, which relates to the technical field of displaying. The displaying device can ameliorate the problem of screen greening caused by electrostatic charges, thereby improving the effect of displaying. The displaying base plate includes an active area and a non-active area connected to the active area, the non-active area includes an edge region and a first-dam region, and the first-dam region is located between the active area and the edge region; the displaying base plate further includes: a substrate; an anti-static layer disposed on the substrate, wherein the anti-static layer is located at least within the edge region; and a driving unit and a touch unit that are disposed on the substrate, wherein the driving unit is located within the active area.

Abstract: Embodiments of the disclosure provide a method and apparatus for running a service, and an electronic device. An embodiment of the method includes: determining a target deployment manner of a graphics processing unit (GPU) according to performance data of each service in a service set, where the deployment manner includes: dividing the GPU into sub-GPUs of a respective size and determining a service configured to be run by each sub-GPU; and switching, for the service in the service set, running of the service from a sub-GPU indicated by a current deployment manner to a sub-GPU indicated by the target deployment manner. According to the embodiment, waste of the GPU can be reduced by running a plurality of services on the GPU.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may detect a trigger event associated with a satellite communication link, the trigger event being based at least in part on at least one of: a status of an access link associated with the UE, or information associated with another device or a component of the UE. The UE may transmit a communication via the satellite communication link based at least in part on detecting the trigger event. Numerous other aspects are described.