Abstract: Techniques are provided herein for forming thin film transistor (TFT) structures having one or more doped contact regions. The addition of certain dopants can be used to increase conductivity and provide higher thermal stability in the contact regions of the TFT. Memory structures having TFT structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the TFT structures within the memory structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region.

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region.

Abstract: Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.

Abstract: Techniques are provided herein for forming thin film transistor structures having a laterally recessed gate electrode. The gate electrode may be recessed such that it does not extend under one or both conductive contacts of the transistor. Recessing the lateral dimensions of the gate electrode can reduce gate leakage current and parasitic capacitance. According to an example, a given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. According to some such embodiments, the memory cells are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory cell arrays are formed within the interconnect region. Any of the given TFT structures may include a gate electrode that is laterally recessed such that one or more of the contacts are not directly over the gate electrode.

Abstract: Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.

Abstract: Techniques are provided for making asymmetric contacts to improve the performance of thin film transistors (TFT) structures. The asymmetry may be with respect to the area of contact interface with the semiconductor region and/or the depth to which the contacts extend into the semiconductor region. According to some embodiments, the TFT structures are used in memory structures arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include asymmetric contacts, such as two contacts that each have a different contact area to a semiconductor region, and/or that extend to different depths within the semiconductor region. The degree of asymmetry may be tuned during fabrication to modulate certain transistor parameters such as, for example, leakage, capacitance, gate control, channel length, or contact resistance.

Abstract: Co-manipulation robotic systems are described herein that may be used for assisting with laparoscopic surgical procedures. The co-manipulation robotic systems allow a surgeon to use commercially-available surgical tools while providing benefits associated with surgical robotics. Advantageously, the surgical tools may be seamlessly coupled to the robot arms using a disposable coupler while the reusable portions of the robot arm remain in a sterile drape. Further, the co-manipulation robotic system may operate in multiple modes to enhance usability and safety, while allowing the surgeon to position the instrument directly with the instrument handle and further maintain the desired position of the instrument using the robot arm.

Abstract: A semiconductor structure includes: a substrate; channel structures on the substrate, a channel structure of the channel structures including a plurality of channel layers stacked along a direction perpendicular to a surface of the substrate and a plurality of gate grooves between adjacent channel layers; gate structures spanning the channel structure, the gate structures being also in the plurality of gate grooves; source/drain regions on the substrate on two sides of the gates and the channel layers, the source/drain regions being in contact with sidewalls of a plurality of channel layers; and inner spacer layers between adjacent channel layers, and first dielectric layers between the inner spacer layers and the gate structures, the inner spacer layers being between the source/drain regions and the gate structures.

Abstract: Co-manipulation robotic systems are described herein that may be used for assisting with laparoscopic surgical procedures. The co-manipulation robotic systems allow a surgeon to use commercially-available surgical tools while providing benefits associated with surgical robotics. Advantageously, the surgical tools may be seamlessly coupled to the robot arms using a disposable coupler while the reusable portions of the robot arm remain in a sterile drape. Further, the co-manipulation robotic system may operate in multiple modes to enhance usability and safety, while allowing the surgeon to position the instrument directly with the instrument handle and further maintain the desired position of the instrument using the robot arm.

Abstract: Co-manipulation robotic systems are described herein that may be used for assisting with laparoscopic surgical procedures. The co-manipulation robotic systems allow a surgeon to use commercially-available surgical tools while providing benefits associated with surgical robotics. Advantageously, the surgical tools may be seamlessly coupled to the robot arms using a disposable coupler while the reusable portions of the robot arm remain in a sterile drape. Further, the co-manipulation robotic system may operate in multiple modes to enhance usability and safety, while allowing the surgeon to position the instrument directly with the instrument handle and further maintain the desired position of the instrument using the robot arm.

Abstract: An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.

Abstract: A semiconductor structure includes a substrate, a plurality of gates, a cut isolation structure, and an interlayer dielectric layer. The plurality of gates are formed on the substrate. The plurality of gates extend along a first direction. The cut isolation structure is formed on the substrate. The cut isolation structure passes through the gates in a second direction. A size of the cut isolation structure in the first direction is equal to a predetermined size. The second direction is different from the first direction. The interlayer dielectric layer is formed on the substrate. The interlayer dielectric layer surrounds the gates and the cut isolation structure.

Abstract: Co-manipulation robotic systems are described herein that may be used for assisting with laparoscopic surgical procedures. The co-manipulation robotic systems allow a surgeon to use commercially-available surgical tools while providing benefits associated with surgical robotics. Advantageously, the surgical tools may be seamlessly coupled to the robot arms using a disposable coupler while the reusable portions of the robot arm remain in a sterile drape. Further, the co-manipulation robotic system may operate in multiple modes to enhance usability and safety, while allowing the surgeon to position the instrument directly with the instrument handle and further maintain the desired position of the instrument using the robot arm.

Abstract: A sensor assembly includes a cover layer and a first sensor apparatus. The cover layer is molded from a first material to have a planar surface and non-uniform thickness, where a thickness of the first material at a first region of the cover layer is less than a thickness of the first material surrounding the first region. The first sensor apparatus is disposed beneath the planar surface of the cover layer, within the first region. The first sensor apparatus is configured to transmit and receive first capacitive sensing signals through a portion of the planar surface coinciding with the first region. For example, the first sensor apparatus may be a fingerprint sensor configured to detect a fingerprint on the portion of the planar surface coinciding with the first region based on changes in the first capacitive sensing signals.

Abstract: An envelope detection circuit and methods for detecting an envelope of a signal using such an envelope detection circuit. One example envelope detection circuit generally includes a first diode, a capacitive element, and a clamping circuit. The first diode has an anode coupled to an input node of the envelope detection circuit and has a cathode coupled to an output node of the envelope detection circuit. The capacitive element is coupled in shunt between the output node and a reference potential node, and the clamping circuit is coupled in shunt between the input node and the reference potential node. The clamping circuit generally includes a resistive element coupled in series with a second diode.

Abstract: The present implementations relate to a support structure for an input device that supports deflection of an input surface responsive to input forces exerted thereon and vibration of the input surface responsive to haptic feedback generated by a haptic actuator. The support structure includes one or more fixed structures mounted to a housing and a dynamic surface mounted to a sensor layer of the input device. A number of first deformable segments cantilever from the one or more fixed surfaces and deflect in a vertical direction when an input force is exerted on the sensor layer, where the input force is orthogonal to the input surface. A number of second deformable segments connect the plurality of first deformable segments to the dynamic surface and deflect in a horizontal direction when shear forces are exerted on the dynamic surface, where the shear forces are parallel to the input surface.

Abstract: Co-manipulation robotic systems are described herein that may be used for assisting with laparoscopic surgical procedures. The co-manipulation robotic systems allow a surgeon to use commercially-available surgical tools while providing benefits associated with surgical robotics. Advantageously, the surgical tools may be seamlessly coupled to the robot arms using a disposable coupler while the reusable portions of the robot arm remain in a sterile drape. Further, the co-manipulation robotic system may operate in multiple modes to enhance usability and safety, while allowing the surgeon to position the instrument directly with the instrument handle and further maintain the desired position of the instrument using the robot arm.

Abstract: A sensor assembly includes a cover layer and a first sensor apparatus. The cover layer is molded from a first material to have a planar surface and non-uniform thickness, where a thickness of the first material at a first region of the cover layer is less than a thickness of the first material surrounding the first region. The first sensor apparatus is disposed beneath the planar surface of the cover layer, within the first region. The first sensor apparatus is configured to transmit and receive first capacitive sensing signals through a portion of the planar surface coinciding with the first region. For example, the first sensor apparatus may be a fingerprint sensor configured to detect a fingerprint on the portion of the planar surface coinciding with the first region based on changes in the first capacitive sensing signals.

Abstract: Certain aspects of the present disclosure provide techniques for determining a cable loss associated with a transmission cable of an apparatus. An example method includes sending, to a radio modem of the apparatus, a request for the radio modem to use a target power when sending one or more signals to the signal compensator device for determining a cable loss associated with a transmission cable communicatively coupling the radio modem with the signal compensator device, receiving, at a signal compensator device of the apparatus, the one or more signals from the radio modem sent using the target power, and determining the cable loss associated with the transmission cable based on the one or more signals.