Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, and a conductive filler. The polymer matrix has a fluoropolymer. The total volume of the PTC material layer is calculated as 100%, and the fluoropolymer accounts for 47-62% by volume of the PTC material layer. The fluoropolymer has a melt viscosity higher than 3000 Pa·s.

Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a polymer matrix and a first conductive filler. The polymer matrix includes a polyolefin-based polymer and a fluoropolymer. The fluoropolymer has a melt flow index higher than 1.9 g/10 min, and the polyolefin-based polymer and the fluoropolymer together form an interpenetrating polymer network (IPN). The first conductive filler has a metal-ceramic compound dispersed in the polymer matrix.

Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 48% to 55%. The conductive filler has a metal-ceramic compound.

Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 33% to 42%.

Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.

Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.

Abstract: A compound prism module is provided, including: a first prism, a second prism, and an interface filling medium. The first prism has a first light-incident surface, a first reflecting surface, and a first light-emitting surface, where the first light-incident surface and the first light-emitting surface are connected to a first side edge, and the first light-incident surface and the first reflecting surface are connected to a first chamfered plane. The second prism has a second light-incident surface, a second reflecting surface, and a second light-emitting surface, wherein the second light-incident surface and the second light-emitting surface are connected to a second side edge, and the second light-incident surface and the second reflecting surface are connected to a second chamfered plane. The first light-incident surface and the second light-incident surface are connected to each other, and the first side edge and the second side edge are parallel to each other.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.

Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

Abstract: A metal-insulator-metal (MIM) capacitor and methods of forming the same are described. In some embodiments, the method includes forming an opening having a first depth in one or more dielectric layers, depositing a layer in the opening and on the one or more dielectric layers, performing an anisotropic etch process to remove portions of the layer formed on horizontal surfaces, extending the opening to a second depth in the one or more dielectric layers, removing the layer, extending the opening to a third depth in the one or more dielectric layers, and forming a MIM capacitor in the opening.

Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a laminated capacitor dielectric layer including alternating layers of high-k dielectric material and high-energy band gap material, and a method of formation. In some embodiments, the MIM capacitor has a laminated capacitor dielectric layer disposed over a capacitor bottom metal layer. The laminated capacitor dielectric layer includes a first layer of a first dielectric material, a second layer of a second dielectric material disposed on top of the first layer, a third layer of a third dielectric material disposed on top of the second layer, and a fourth layer of a fourth dielectric material disposed on top of the third layer. The first and third dielectric materials have a differing capacitance and band gap energy as compared to the second and fourth dielectric materials. A capacitor top metal layer is disposed over the laminated capacitor dielectric layer.

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a laminated capacitor dielectric layer including alternating layers of high-k dielectric material and high-energy band gap material, and a method of formation. In some embodiments, the MIM capacitor has a laminated capacitor dielectric layer disposed over a capacitor bottom metal layer. The laminated capacitor dielectric layer includes a first layer of a first dielectric material, a second layer of a second dielectric material disposed on top of the first layer, a third layer of a third dielectric material disposed on top of the second layer, and a fourth layer of a fourth dielectric material disposed on top of the third layer. The first and third dielectric materials have a differing capacitance and band gap energy as compared to the second and fourth dielectric materials. A capacitor top metal layer is disposed over the laminated capacitor dielectric layer.

Abstract: An embodiment semiconductor wafer includes a bottom semiconductor layer having a first doping concentration, a middle semiconductor layer over the bottom semiconductor layer, and a top semiconductor layer over the middle semiconductor layer. The middle semiconductor layer has a second doping concentration greater than the first doping concentration, and the top semiconductor layer has a third doping concentration less than the second doping concentration. A lateral surface of the bottom semiconductor layer is an external surface of the semiconductor wafer, and sidewalls of the bottom semiconductor layer, the middle semiconductor layer, and top semiconductor layer are substantially aligned.

Abstract: An embodiment semiconductor wafer includes a bottom semiconductor layer having a first doping concentration, a middle semiconductor layer over the bottom semiconductor layer, and a top semiconductor layer over the middle semiconductor layer. The middle semiconductor layer has a second doping concentration greater than the first doping concentration, and the top semiconductor layer has a third doping concentration less than the second doping concentration. A lateral surface of the bottom semiconductor layer is an external surface of the semiconductor wafer, and sidewalls of the bottom semiconductor layer, the middle semiconductor layer, and top semiconductor layer are substantially aligned.