Patents by Inventor Cheng-Tien Wan

Cheng-Tien Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916108
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: February 27, 2024
    Assignee: MediaTek Inc.
    Inventors: Cheng-Tien Wan, Ming-Cheng Lee
  • Publication number: 20230178607
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 8, 2023
    Applicant: Media Tek Inc.
    Inventors: Cheng-Tien Wan, Ming-Cheng Lee
  • Patent number: 11600700
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: March 7, 2023
    Assignee: MediaTek Inc.
    Inventors: Cheng-Tien Wan, Ming-Cheng Lee
  • Publication number: 20220406921
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Application
    Filed: August 22, 2022
    Publication date: December 22, 2022
    Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
  • Publication number: 20220336680
    Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 20, 2022
    Applicant: MediaTek Inc.
    Inventors: Cheng-Tien Wan, Ming-Cheng Lee
  • Patent number: 11450756
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: September 20, 2022
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Tien Wan, Yao-Tsung Huang, Yun-San Huang, Ming-Cheng Lee, Wei-Che Huang
  • Patent number: 11404587
    Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 2, 2022
    Assignee: MediaTek Inc.
    Inventors: Cheng-Tien Wan, Ming-Cheng Lee
  • Publication number: 20220052160
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.
    Type: Application
    Filed: October 28, 2021
    Publication date: February 17, 2022
    Applicant: MediaTek Inc.
    Inventors: Cheng-Tien Wan, Ming-Cheng Lee
  • Patent number: 11189694
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: November 30, 2021
    Assignee: MediaTek Inc.
    Inventors: Cheng-Tien Wan, Ming-Cheng Lee
  • Publication number: 20210135016
    Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.
    Type: Application
    Filed: September 18, 2020
    Publication date: May 6, 2021
    Inventors: Cheng-Tien WAN, Ming-Cheng LEE
  • Publication number: 20200388700
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
  • Patent number: 10790380
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 29, 2020
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Tien Wan, Yao-Tsung Huang, Yun-San Huang, Ming-Cheng Lee, Wei-Che Huang
  • Publication number: 20200135859
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 30, 2020
    Applicant: MediaTek Inc.
    Inventors: Cheng-Tien Wan, Ming-Cheng Lee
  • Publication number: 20190123176
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Application
    Filed: September 5, 2018
    Publication date: April 25, 2019
    Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
  • Patent number: 10084069
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Patent number: 9922828
    Abstract: A method comprises performing a surface treatment on a plurality of recesses in a substrate to form a first cloak-shaped recess, a second cloak-shaped recess and a third cloak-shaped recess, wherein each cloak-shaped recess is between two isolation regions over the substrate and growing a semiconductor material in the first cloak-shaped recess, the second cloak-shaped recess and the third cloak-shaped recess to form a first cloak-shaped active region, a second cloak-shaped active region and a third cloak-shaped active region, wherein the first cloak-shaped active region has a first non-planar top surface, the second cloak-shaped active region has a second non-planar top surface and the third cloak-shaped active region has a third non-planar top surface.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Publication number: 20170309730
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Patent number: 9722051
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Publication number: 20170133225
    Abstract: A method comprises performing a surface treatment on a plurality of recesses in a substrate to form a first cloak-shaped recess, a second cloak-shaped recess and a third cloak-shaped recess, wherein each cloak-shaped recess is between two isolation regions over the substrate and growing a semiconductor material in the first cloak-shaped recess, the second cloak-shaped recess and the third cloak-shaped recess to form a first cloak-shaped active region, a second cloak-shaped active region and a third cloak-shaped active region, wherein the first cloak-shaped active region has a first non-planar top surface, the second cloak-shaped active region has a second non-planar top surface and the third cloak-shaped active region has a third non-planar top surface.
    Type: Application
    Filed: January 20, 2017
    Publication date: May 11, 2017
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Patent number: 9559099
    Abstract: A FinFET device comprises an isolation region in a substrate, wherein the isolation region comprises a plurality of non-vertical sidewalls, a first V-shaped groove, a second V-shaped groove and a third V-shaped groove formed in the substrate, a first cloak-shaped active region over the first V-shaped groove, wherein a top surface of the first cloak-shaped active region comprises a first slope, a second cloak-shaped active region over the second V-shaped groove, wherein a top surface of the second cloak-shaped active region is triangular in shape and a third cloak-shaped active region over the third V-shaped groove, wherein a top surface of the third cloak-shaped active region comprises a second slope.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko