Patents by Inventor Cheng-Tien Wan
Cheng-Tien Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923460Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.Type: GrantFiled: June 28, 2022Date of Patent: March 5, 2024Assignee: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Patent number: 11916108Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.Type: GrantFiled: January 30, 2023Date of Patent: February 27, 2024Assignee: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Publication number: 20230178607Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.Type: ApplicationFiled: January 30, 2023Publication date: June 8, 2023Applicant: Media Tek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Patent number: 11600700Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.Type: GrantFiled: October 28, 2021Date of Patent: March 7, 2023Assignee: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Publication number: 20220406921Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.Type: ApplicationFiled: August 22, 2022Publication date: December 22, 2022Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
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Publication number: 20220336680Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.Type: ApplicationFiled: June 28, 2022Publication date: October 20, 2022Applicant: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Patent number: 11450756Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.Type: GrantFiled: August 25, 2020Date of Patent: September 20, 2022Assignee: MEDIATEK INC.Inventors: Cheng-Tien Wan, Yao-Tsung Huang, Yun-San Huang, Ming-Cheng Lee, Wei-Che Huang
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Patent number: 11404587Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.Type: GrantFiled: September 18, 2020Date of Patent: August 2, 2022Assignee: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Publication number: 20220052160Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.Type: ApplicationFiled: October 28, 2021Publication date: February 17, 2022Applicant: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Patent number: 11189694Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.Type: GrantFiled: October 1, 2019Date of Patent: November 30, 2021Assignee: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Publication number: 20210135016Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.Type: ApplicationFiled: September 18, 2020Publication date: May 6, 2021Inventors: Cheng-Tien WAN, Ming-Cheng LEE
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Publication number: 20200388700Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.Type: ApplicationFiled: August 25, 2020Publication date: December 10, 2020Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
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Patent number: 10790380Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.Type: GrantFiled: September 5, 2018Date of Patent: September 29, 2020Assignee: MEDIATEK INC.Inventors: Cheng-Tien Wan, Yao-Tsung Huang, Yun-San Huang, Ming-Cheng Lee, Wei-Che Huang
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Publication number: 20200135859Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.Type: ApplicationFiled: October 1, 2019Publication date: April 30, 2020Applicant: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Publication number: 20190123176Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.Type: ApplicationFiled: September 5, 2018Publication date: April 25, 2019Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
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Patent number: 10084069Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.Type: GrantFiled: July 12, 2017Date of Patent: September 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
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Patent number: 9922828Abstract: A method comprises performing a surface treatment on a plurality of recesses in a substrate to form a first cloak-shaped recess, a second cloak-shaped recess and a third cloak-shaped recess, wherein each cloak-shaped recess is between two isolation regions over the substrate and growing a semiconductor material in the first cloak-shaped recess, the second cloak-shaped recess and the third cloak-shaped recess to form a first cloak-shaped active region, a second cloak-shaped active region and a third cloak-shaped active region, wherein the first cloak-shaped active region has a first non-planar top surface, the second cloak-shaped active region has a second non-planar top surface and the third cloak-shaped active region has a third non-planar top surface.Type: GrantFiled: January 20, 2017Date of Patent: March 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
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Publication number: 20170309730Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.Type: ApplicationFiled: July 12, 2017Publication date: October 26, 2017Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
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Patent number: 9722051Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.Type: GrantFiled: September 4, 2015Date of Patent: August 1, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
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Publication number: 20170133225Abstract: A method comprises performing a surface treatment on a plurality of recesses in a substrate to form a first cloak-shaped recess, a second cloak-shaped recess and a third cloak-shaped recess, wherein each cloak-shaped recess is between two isolation regions over the substrate and growing a semiconductor material in the first cloak-shaped recess, the second cloak-shaped recess and the third cloak-shaped recess to form a first cloak-shaped active region, a second cloak-shaped active region and a third cloak-shaped active region, wherein the first cloak-shaped active region has a first non-planar top surface, the second cloak-shaped active region has a second non-planar top surface and the third cloak-shaped active region has a third non-planar top surface.Type: ApplicationFiled: January 20, 2017Publication date: May 11, 2017Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko